基于NX软件平台的多轴加工编程刀具路径优化方法研究

本文基于西门子NX软件多轴编程模块,首先针对编程工艺人员经常出现的四轴刀路转弯处“跳刀”现象和五轴曲面加工“流曲线”不规则的问题,给出了常规解决方案;其次,为以上两个问题提出了一种全新的解决方案,通过与常规方案的对比,分析其生成的刀具路径效果,并通过实际上机加工验证了新方案的可行性。方法源于实践经验,可极大的提升加工效率,提高加工质量,对多轴编程工艺人员具有一定参考价值。     

基于多通信方式实现DSP程序在线编程

该文针对基于DSP的野外及外场数字设备更新升级提出了一种基于多通信方式的DSP程序在线编程的新方法.该方法同时具备有线、无线多种通信能力,可以根据具体环境灵活选择.使用可扩展通信协议栈,支持对通信接口和通信协议的扩展.程序更新基于DSP/BIOS实时操作系统,根据预设算法,更新指定存储区的可执行程序,实现对原程序替换和升级.实践表明,把该方法应用于系统的目标程序在线编程,程序功能稳定可靠,使DSP程序的更新脱离了仿真器,满足了现场更新的时效性、可扩展性和便携性要求.     

一种串并结合的多Site熔丝编程算法

随着集成电路产业的迅猛发展,熔丝修调越来越广泛地应用于集成电路测试工序,熔丝段数目随着需要修调参数的增多而逐步增长,传统的串行熔丝编程方案程序存在代码长、可维护性差、执行时间长等缺点,为了改进代码的可读性和可维护性,文章引进了改进型算法,但对测试执行时间没有任何改善。随着测试代工市场竞争日益激烈,多Site测试方案被广泛使用,但是熔丝编程还继续着串行编程的老算法,Site数目越多,熔丝编程时间越长。针对以上,文章提出了一种串并结合的多Site熔丝编程算法,将多Site熔丝编程时间控制在和单Site熔丝串行编程时间几乎一致。     

基于多阶段攻击的网络安全风险评估方法

网络安全风险评估技术能够检测网络系统潜在的安全漏洞和脆弱性，评估网络系统的安全状况，是实现网络安全的重要技术之一．文中对基于多阶段攻击的网络安全风险评估方法进行了研究，给出了多阶段攻击的网络安全风险评估方法的评估过程，分析了该评估方法中的关键参数，构建了基于多阶段攻击的网络安全风险评估的模型，最后通过实践验证了该方法的有效性，一定程度上提高了评估结果的准确性和一致性。     

新颖多花样大功率编程彩灯控制器

<正> 本文介绍一种最新彩灯控制专用集成电路SE9518,它可以广泛用于门面店铺灯光装璜,节日彩灯装饰,舞厅、咖啡厅、酒吧间、大型彩灯广告以及作摩托车尾箱、汽车刹车等的灯光装饰,而且特别适合于作霓虹灯的花样控制器。它的八种基本花样,经编程端编程后,即可得到二十七种不同组合。该电路既可单片使用,亦可多片级联,因而用户在花样上亦可自行创新,趣味无穷。     

基于NX的端盖零件三维建模与CAM编程

文章基于对典型端盖零件的数控加工工艺分析,完成端盖零件的数控加工工艺设计,然后使用NX软件完成端盖零件的三维数字模型的建模及数控加工工艺中的CAM自动编程,文章重点探讨如何进行零件的三维模型建立和CAM编程,包括常用的建模思路和如何进行建模,CAM编程中主要探讨数控车削加工中外圆柱表面的加工和数控铣削加工中的常用加工方式,通过完成这个流程进一步掌握零件的三维建模和CAM编程的基本过程。     

一种简化的多阶段译码结构

通过分析MSD和PDL两种译码方法在等价调制容量计算上的异同点及其与映射方法之间的关系，提出了几种新的针对8PSK和16QAM的信号星座映射图，按此进行映射设计，可以将MSD译码结构部分地用并行结构来实现，从而简化了系统的译码算法，降低了系统的译码时延。仿真结果表明：改进的MSD结构不会带来系统在性能上的损失，相反在低信嗓比情况下，由于错误传播现象的消除而使系统的性能有所提高，结果可直接推广到其它高维MPSK和MQAM信号空间。     

基于多阶段学习的相关滤波目标跟踪

由于跟踪过程中目标外观变化和遮挡因素的影响,采用单一迭代更新滤波器的KCF算法在学习过程中会积累过多的噪声信息导致目标丢失.为解决该问题,本文提出一种基于多阶段学习的相关滤波跟踪算法.通过建立具有互补关系的全局阶段滤波器模型、一致性阶段滤波器模型以及初始阶段滤波器模型并行的对目标进行跟踪.在benchmark数据集的51个视频上的实验表明,本文算法取得的总体精度得分77.6%和总体成功率得分68.9%优于现有的大部分跟踪算法.     

TSB:一种多阶段IPv6路由表查找算法

充分分析IPv6地址结构、IPv6地址分配策略和IPv6骨干网路由表的特点后,将二叉树、段表和路由桶技术相结合,提出一种多阶段IPv6路由表查找算法.和已有算法相比,提出的算法查找速度快、占用内存少、扩展性好、支持增量更新.实验结果表明算法的软件参考实现在装有P4 2.4GHz CPU,512M DDR333 内存和Linux 操作系统的普通PC 机上的查找能力可以到达16MPPS(Million Packet per Second),这可以满足10Gbps 80 字节IPv6最小包的线速转发.对于当前IPv6骨干网BGP 路由表,算法的参考实现只占用几百K 字节的内存.     

Fault tolerance of on-board digital signal processing circuits

The paper is organized in four sections. The first section introduces the nature of faults as well as their causes. The methods used to identify faults and the actions necessary to correct the situation are outlined. The second section identifies the different fault tolerance approaches to conventional computational circuits and the DSP circuits. Current research work in the area of fault tolerance of FFT, signal processing and VLSI circuits involving systolic arrays is reviewed. Since some of the techniques do not involve error correction, reconfiguration of the circuit after error detection becomes necessary and a brief look at the relevant reconfiguration strategies is appropriate. Software fault tolerance is introduced and some work applicable to computations in general is reviewed. The implementation of the methods and its consequences are described in the third section. Concluding remarks form the final section.     

Error-feedback circuits for digital filters

Criteria are developed for the design of a very general error-feedback circuit whose purpose is to eliminate the presence of nonlinear phenomena, caused by the occurrence of adder overflows, in the forced response of a 2nd-order recursive digital filter.     

Statistical RTS model for digital circuits

In this work we study the variation in drain current of MOS transistors due to the capture and emission of electrons at interface states (traps), called random telegraph signal (RTS). Usually, RTS is studied in frequency domain. However, for digital circuits, it is more appropriate to use time-domain representations.The time-domain representation here proposed models the effect of RTS on I_ds as instantaneous Vt shifts. We introduce a statistical numerical approach for computing the total ΔVt of the transistor considering all the traps in the interface. The method analyses the effect of non-uniform charge densities along the channel. To show the applicability of the methodology to circuit analysis on the electrical level, the model is applied to characterize read and write instability failures caused by RTS on a 6T-SRAM cell.     

Timing circuits for RSFQ digital systems

A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm². The most complex clock controller generates trains of 2²⁴ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6×10^-5 . The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz     

Linear programming for hazard elimination in asynchronous circuits

Hazards can be globally eliminated from an asynchronous circuit synthesized from a Signal Transition Graph by repeatedly solving an appropriate Linear Program. This article describes how to analyze the STG specification and the synthesized circuit, using bounded delay information, to formulate the problem and use a branch-and-bound procedure to solve it. Known information about the environment delays can be expressed as time bounds on the external signal transitions, and it can be exploited by the proposed methodology.     

Compaction-based concurrent error detection for digital circuits

We present a non-intrusive concurrent error detection (CED) method for combinational and sequential digital circuits. We analyze the optimal solution model and point out the limitations that prevent logic synthesis from yielding a minimal-cost monolithic CED implementation. We then propose a compaction-based alternative approach for restricted error models. The proposed method alleviates these limitations by decomposing the CED functionality into: compaction of the circuit outputs, prediction of the compacted responses, and comparison. We model the fault-free and erroneous responses as connected vertices in a graph and perform graph coloring in order to derive the compacted responses. The proposed method is first discussed within the context of combinational circuits, with zero detection latency, and subsequently extended to Finite State Machines (FSMs), with a constant detection latency of one clock cycle. Experimental results demonstrate that the proposed method achieves significant hardware reduction over duplication-based CED, while detecting all possible errors.     

Built-in test for complex digital integrated circuits

A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).     

Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm ². The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns     

Adaptively designed test logic for digital circuits

Adaptive n-tuple pattern-recognition techniques in their hardware embodiment may be used to design test circuits for logic systems which indicate the presence of a fault. The principles of this concept are explained and early results obtained with realistically scaled circuits are presented.