Interfacial structure and electrical properties of LaAlO3 gate dielectric films on Si by metalorganic chemical vapor deposition

LaAlO₃ (LAO) gate dielectric films were deposited on Si substrates by low-pressure metalorganic chemical vapor deposition. The interfacial structure and composition distribution were investigated by high-resolution transmission electron microscopy (HRTEM), X-ray photoelectron spectroscopy (XPS), secondary-ion mass spectroscopy (SIMS), and Auger-electron spectroscopy (AES). HRTEM confirms that there exists an interfacial layer between LAO and Si in most samples. AES, SIMS, and XPS analyses indicate that the interfacial layer is compositionally graded La–Al silicate and the Al element is severely deficient close to the Si surface. Electrical properties of LAO films were evaluated. No evident difference in electrical properties between samples with and without native SiO₂ layers was observed. The electrical properties are discussed in terms of LAO growth mechanisms, in relation to the interfacial structure. PACS 73.40.Qv; 81.15.Gh; 77.55.+f; 68.35.-p     

Valence band variation in Si (110) nanowire induced by a covered insulator

In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k$\cdot$p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO₂ insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO₂ insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO₂ insulator, the strain of the HfO₂ gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO₂ insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.     

异质多晶SiGe栅应变Si NMOSFET物理模型研究

结合了“栅极工程”和“应变工程”二者的优点, 异质多晶SiGe栅应变Si MOSFET, 通过沿沟道方向使用不同功函数的多晶SiGe材料, 在应变的基础上进一步提高了MOSFET的性能. 本文结合其结构模型, 以应变Si NMOSFET为例, 建立了强反型时的准二维表面势模型, 并进一步获得了其阈值电压模型以及沟道电流的物理模型. 应用MATLAB对该器件模型进行了分析, 讨论了异质多晶SiGe栅功函数及栅长度、衬底SiGe中Ge组分等参数对器件阈值电压、沟道电流的影响, 获得了最优化的异质栅结构. 模型所得结果与仿真结果及相关文献给出的结论一致, 证明了该模型的正确性. 该研究为异质多晶SiGe栅应变Si MOSFET的设计制造提供了有价值的参考. 关键词： 异质多晶SiGe栅 应变Si NMOSFET 表面势 沟道电流     

Influence of excess Si distribution in the gate oxide on the memory characteristics of MOSFETs

In this work, Si ions are implanted into the gate oxide of MOSFETs with different implantation schemes, followed by a high-temperature annealing. The memory characteristics of the MOSFETs have been investigated for the following two excess Si distributions: (1) the excess Si is distributed in a narrow layer in the gate oxide near the Si substrate; and (2) the excess Si is distributed throughout the gate oxide. It is observed that both the excess Si distributions have good endurance of up to 10⁶ program/erase cycles. The second excess Si distribution exhibits a better retention characteristic with less than 50% charge loss after 10 years. In contrast, the first excess Si distribution shows a complete charge loss after 1 year. PACS 73.22.-f; 73.63.Bd; 81.07.Bc     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

Strain in Ultrathin SiGeSn Layers in a Silicon Matrix

Strain in SiGeSn alloy layers with thicknesses of d = 1.5 and 2.0 nm grown in a Si matrix by molecular-beam epitaxy is investigated using the geometric-phase analysis of high-resolution electron microscopy images. The layer thickness is comparable to the spatial resolution of the method (Δ ~ 1 nm), which leads to a considerable distortion of the strain distribution profile and an error in determining the strain value. A correction to the measured strain making it closer to the true value is obtained by comparing the shapes of the observed and real strain distributions in the investigated layers. The correction is determined by the Δ/d ratio. The found strain values are in good agreement with the calculations for pseudomorphic layers in the model of a rigid substrate.     

Characterization of {111} planar defects induced in silicon by hydrogen plasma treatments

Microstructural characterization by transmission electron microscopy of the {111} planar defects induced in Si by treatment in hydrogen plasma is discussed. The {111} defects are analyzed by conventional (TEM) and high-resolution transmission electron microscopy (HRTEM). Quantitative image processing by the geometrical phase method is applied to the experimental high-resolution image of an edge-on oriented {111} defect to measure the local displacements and strain field around it. Using these data, a structural model of the defect is derived. The validity of the structural model is checked by high-resolution image simulation and comparison with experimental images.     

Surface and interfacial structural characterization of MBE grown Si/Ge multilayers

Si/Ge multilayer structures have been grown by solid source molecular beam epitaxy (MBE) on Si (1 1 1) and (1 0 0) substrates and were characterized by high-resolution X-ray diffraction (XRD), atomic force microscopy (AFM), high-depth-resolution secondary ion mass spectroscopy (SIMS) and cross-section high-resolution transmission electron microscopy (HRTEM). A reasonably good agreement has been obtained for layer thickness, interfacial structure and diffusion between SIMS and HRTEM measurements. Epitaxial growth and crystalline nature of the individual layer have been probed using cross-sectional HRTEM and XRD measurements. Surface and interface morphological studies by AFM and HRTEM show island-like growth of both Si and Ge nanostructures.     

The effect of Si surface nitridation on the interfacial structure and electrical properties of (La2O3)0.5(SiO2)0.5 high-k gate dielectric films

Thermal stability, interfacial structures and electrical properties of amorphous (La₂O₃)_0.5(SiO₂)_0.5 (LSO) films deposited by using pulsed laser deposition (PLD) on Si (1 0 0) and NH₃ nitrided Si (1 0 0) substrates were comparatively investigated. The LSO films keep the amorphous state up to a high annealing temperature of 900 °C. HRTEM observations and XPS analyses showed that the surface nitridation of silicon wafer using NH₃ can result in the formation of the passivation layer, which effectively suppresses the excessive growth of the interfacial layer between LSO film and silicon wafer after high-temperature annealing process. The Pt/LSO/nitrided Si capacitors annealed at high temperature exhibit smaller CET and EOT, a less flatband voltage shift, a negligible hysteresis loop, a smaller equivalent dielectric charge density, and a much lower gate leakage current density as compared with that of the Pt/LSO/Si capacitors without Si surface nitridation.     

Metal-semiconductor nanocontacts: silicon nanowires

Strain evolution of coherent Ge islands on Si(001) is measured using a newly developed transmission electron microscopy technique based on two-beam dark-field strain imaging. The strain measurements show that a metastable Ge island shape is involved in the shape transition between pyramids and domes; this shape is more readily observed for growth at 550 than 600 degrees C because of the slower rate at which islands cross the kinetic barrier between shapes. The strain relaxation changes discontinuously between pyramids and domes, indicating that the underlying shape transition is first order.     

Observation of defects and growth orientations of YBa2Cu3Ox thin films with YSZ buffer layers on Si

We have investigated defects and in-plate orientations of YBa₂Cu₃O_x thin films prepared by pulsed laser deposition (PLD) with YSZ as a buffer layer. The films showed c-axis oriented growth with the transition temperature T_co up to 87 K. Several types of defects including thermally induced cracks, grain boundaries and outgrowths were observed by scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HRTEM). The grain boundary provided a favorable path for crack propagation. The outgrowths nucleated on the YSZ surface grew with stoichiometric composition. According to X-ray diffraction (XRD) and HRTEM studies the YSZ buffer layer grew with the orientation relationship, YSZ110//Si110 and YSZ(001)//Si(001) up to the YBCO/YSZ interface. The superconducting YBCO films on top grew mainly with YBCO100//Si110 and YBCO(001)//Si(001), with some minor portions of YBCO110//Si110 and YBCO(001)//Si(001).     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

Characterization of gadolinium oxide film by pulse laser deposition

In this work, Gd-oxide dielectric films were deposited on Si by pulse laser deposition method (PLD), moreover, the micro-structures and electrical properties were reported. High-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) indicated that Gd-oxide was polycrystalline Gd₂O₃ structure, and no Gd metal phase was detected. In addition, both interface at Si and Ni fully silicide (FUSI) gate were smooth without the formation of Si-oxide. X-ray photoelectron spectroscopy (XPS) confirmed the formation of Gd₂O₃ and gave an atom ratio of 1:1 for Gd:O, indicating O vacancies existed in Gd₂O₃ polycrystal matrix even at O₂ partial pressure of 20 mTorr. Electrical measurements indicated that the dielectric constant of Gd-oxide film was 6 and the leakage current was 0.1 A/cm² at gate bias of 1 V.     

Interface strain profiling in ultrathin SiO2 gate oxides with medium energy ion scattering spectroscopy

Medium energy ion scattering spectroscopy (MEIS) could identify ∼1 nm interface layer with compressive strain, which depends sensitively on the interface treatment conditions such as oxynitridation, ozone oxidation, tilt of Si(0 0 1) substrates. The interface strain relaxation always shows improvements in gate oxide reliability. Atomic scale investigations of strain profiles with MEIS are reviewed for SiO₂/Si(0 0 1) interfaces.     

The mobility of electrons in strained silicon

The development of Si and Si_1−xGe_x layer growth by molecular beam epitaxy has enabled heterostructures and HEMT devices to be made with Group IV semiconductors. Strain is very important in determining the electronic behaviour of this system and as an initial step towards understanding mobility in SiGe HEMT structures a Monte Carlo technique has been used to simulate electron transport in bulk Si, strained by commensurate growth on a (001) Si_1−yGe_y buffer. The in-plane mobility initially increases with increasing strain but then falls at higher strains and fields. Results are presented for both undoped and 10¹⁷ cm⁻³ n-type Si, fields of 10² to 10⁴ Vcm⁻¹ and strain levels up to the equivalence of growth on a Si_0.25Ge_0.75 buffer. The results are explained by the splitting of the degenerate conduction band minimum and the transition probability between the two-fold and four-fold split minima.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

Ultrathin gate dielectrics for silicon nanodevices

This paper reviews recent progress in structural and electronic characterizations of ultrathin SiO₂thermally grown on Si(100) surfaces and applications of such nanometer-thick gate oxides to advanced MOSFETs and quantum-dot MOS memory devices. Based on an accurate energy band profile determined for the n ⁺ -poly- Si/SiO₂/Si(100) system, the measured tunnel current through ultrathin gate oxides has been quantitatively explained by theory. From the detailed analysis of MOSFET characteristics, the scaling limit of gate oxide thickness is found to be 0.8 nm. Novel MOSFETs with a silicon quantum-dot floating gate embedded in the gate oxide have indicated the multiple-step electron injection to the dot, being interpreted in terms of Coulombic interaction among charged dots.     

Poly-Si1-xGex栅应变SiN型金属-氧化物-半导体场效应管栅耗尽模型研究

基于对Poly-Si_1-xGe_x栅功函数的分析,通过求解Poisson方程, 获得了Poly-Si_1-xGe_x栅应变Si N型金属-氧化物-半导体场效应器件 (NMOSFET)垂直电势与电场分布模型.在此基础上,建立了考虑栅耗尽的Poly-Si_1-xGe_x栅应变Si NMOSFET的阈值电压模型和栅耗尽宽度及其归一化模型,并利用该模型,对器件几何结构参数、 物理参数尤其是Ge组分对Poly-Si_1-xGe_x栅耗尽层宽度的影响, 以及栅耗尽层宽度对器件阈值电压的影响进行了模拟分析.结果表明:多晶耗尽随Ge组分和栅掺杂浓度的增加而减弱, 随衬底掺杂浓度的增加而增强;此外,多晶耗尽程度的增强使得器件阈值电压增大. 所得结论能够为应变Si器件的设计提供理论依据.     

（110）应变对立方相Ca2Si能带结构及光学性质的影响

采用第一性原理贋势平面波方法对(110)应变下立方相Ca2P0.25Si0.75的能带结构及光学性质进行模拟计算,全面分析了应变对Ca2P0.25Si0.75能带结构、光学性质的影响。计算结果表明：在92%~100%压应变范围内随着应变的逐渐增大导带向低能方向移动,价带向高能方向移动,带隙呈线性逐渐减小,但始终为直接带隙;在100%~102%张应变范围内随着应变的增加,带隙呈逐渐增大,应变达到102%直接带隙最大Eg=0.54378eV;在102%~104%应变范围内随着应变的增加,带隙逐渐减小;当应变大于104%带隙变为间接带隙且带隙随着应变增大而减小。施加应变Ca2P0.25Si0.75的介电常数、折射率均增大;施加压应变吸收系数增加,反射率减小;施加张应变吸收系数减小,反射率增加。综上所述,应变可以改变Ca2P0.25Si0.75的电子结构和光学常数,是调节Ca2P0.25Si0.75光电传输性能的有效手段。     

（110）应变对立方相Ca2Si能带结构及光学性质的影响

采用第一性原理贋势平面波方法对(110)应变下立方相Ca2P0.25Si0.75的能带结构及光学性质进行模拟计算,全面分析了应变对Ca2P0.25Si0.75能带结构、光学性质的影响。计算结果表明：在92%~100%压应变范围内随着应变的逐渐增大导带向低能方向移动,价带向高能方向移动,带隙呈线性逐渐减小,但始终为直接带隙;在100%~102%张应变范围内随着应变的增加,带隙呈逐渐增大,应变达到102%直接带隙最大Eg=0.54378eV;在102%~104%应变范围内随着应变的增加,带隙逐渐减小;当应变大于104%带隙变为间接带隙且带隙随着应变增大而减小。施加应变Ca2P0.25Si0.75的介电常数、折射率均增大;施加压应变吸收系数增加,反射率减小;施加张应变吸收系数减小,反射率增加。综上所述,应变可以改变Ca2P0.25Si0.75的电子结构和光学常数,是调节Ca2P0.25Si0.75光电传输性能的有效手段。