A novel soft-switched PWM current source inverter with voltageclamped circuit

This paper develops a new series resonant (current resonant) DC link inverter with a voltage clamped circuit. The proposed circuit has a fixed pulse frequency operation. The fixed pulse frequency at 20-50 kHz enables the system to work without audible noise, and to involve the much smaller-sized DC inductance and output capacitors compared with hard-switched current source inverters. The proposed circuit has a voltage clamped circuit which could control the voltage stress of the switches. In this paper, explanations of the new circuit configuration, the simulation, design considerations, and some experimental results are included     

A new soft-switched PWM boost converter with a lossless auxiliary circuit

A soft-switching scheme for the PWM boost converter is newly proposed to obtain the desirable features of both the conventional PWM boost and resonant converters such as ease of control, reduced switching losses and stresses, and low EMI. In order to achieve the soft-switching action, the proposed scheme employs an auxiliary circuit, which is added to the conventional boost converter and used to achieve soft-switching for both the main switch and the output diode while not incurring any additional losses due to the auxiliary circuit itself. The basic operations, in this paper, are discussed and design guidelines are presented. Through a 100?KHz, 60?W prototype, the usefulness of the proposed scheme is verified.     

Analysis of a quasi-resonant circuit for soft-switched inverters

This paper presents an analysis of a quasi-resonant circuit for soft-switched inverters. The quasi-resonant circuit provides zero-voltage instants for zero-voltage inverter switching by pulling down the DC link voltage momentarily to zero without increasing the peak value of the nominal DC link voltage. Switches in the quasi-resonant circuit can also be turned off at zero current/voltage conditions. The proposed circuit allows creation of zero voltage conditions for inverter soft-switching under loaded and no-load conditions. The operating principle of this circuit is explained, and the analysis of each operating mode is described. Design criteria for achieving zero voltage switching are derived from the general mathematical analysis. Operation of the circuit has been verified by PSPICE simulation and experiments     

Optimized design of a fully soft-switched boost-converter suitable for power factor correction

A fully soft-switched boost-converter using a one auxiliary switch is presented here. It uses the minimum number of components in the auxiliary circuit with minimum current stress of the main switch. Since the resonant capacitor charges only through an inductor and a diode, the circuit conduction losses are minimized. The main and auxiliary insulated gate bipolar transistor (IGBT) switches share a common emitter connection, facilitating direct drive to them. Various operating modes of the converter are presented in detail and analysed. The choice of the resonating capacitor and inductor has been done through an optimization process based on the guiding equations working under different modes. In this optimization process, emphasis has been given on minimum voltage stress on the auxiliary switch for a wide duty cycle range of operation. Based on the design, the principle of operation has been verified with computer simulation. Experimental results from a laboratory prototype with active power factor correction confirms the operation of this converter.     

A new three-level soft-switched converter

A three-level, constant-frequency, isolated converter which employs a coupled inductor to achieve zero-voltage switching of the primary switches in the entire line and load range is described. Because the coupled inductor does not appear as a series inductance in the load current path, it does not cause a loss of duty cycle or severe voltage ringing across the output rectifiers. The operation and performance of the proposed converter was verified on a 1-kW prototype.     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

A fully integrated CMOS inverse sine circuit for computational systems

An inverse trigonometric function generator using CMOS technology is presented and implemented. The development and synthesis of inverse trigonometric functional circuits based on the simple approximation equations are also introduced. The proposed inverse sine function generator has the infinite input range and can be used in many measurement and instrumentation systems. The nonlinearity of less than 2.8% for the entire input range of 0.5 Vp-p with a small-signal bandwidth of 3.2 MHz is achieved. The chip implemented in 0.25 μm CMOS process operates from a single 1.8 V supply. The measured power consumption and the active chip area of the inverse sine function circuit are 350 μW and 0.15 mm², respectively.     

A soft-switched current-controlled converter for induction machinedrives

The paper proposes a current controlled inverter operating in zero voltage switching (ZVS) mode for an induction machine drive. Operation with no voltage stress in the DC link bus is achieved. Together with the soft switching operation, a fixed frequency bang-bang current control technique is also implemented to allow for an accurate shaping of sinusoidal currents to feed the motor. As a result, a ripple free torque profile in steady state operation is achieved. With the soft switching technique it is possible to operate conventional IGBTs at 40 kHz. A detailed analysis of the circuit operation is presented. The feasibility of the proposed scheme is experimentally verified on a prototype     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A fully differential comparator using a switched-capacitordifferencing circuit with common-mode rejection

A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-μm CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-μm CMOS process, the comparator occupies 0.25 mm² and dissipates 1.05 mW     

High-power-factor soft-switched boost converter

A novel implementation of the high-power-factor (HPF) boost converter with active snubber is described. The snubber circuit reduces the reverse-recovery-related losses of the rectifier and also provides zero-voltage switching for the boost switch and zero-current switching for the auxiliary switch. The performance of the proposed approach was evaluated on an 80-kHz, 1.5-kW, universal-line range, HPF boost converter. The proposed technique improves the efficiency by approximately 2% at full load and low line.     

A novel soft-switched PWM inverter for AC motor drives

A novel soft-switched inverter topology is derived from the passively clamped quasi-resonant link (PCQRL) circuit. By introducing magnetic coupling between the two resonant inductors, the number of auxiliary switches can be reduced from two to one, and only a single magnetic core is required for the resonant DC link. An analysis of this novel PCQRL topology with coupled inductors is presented to reveal the various soft-switching characteristics. In comparison with the conventional passively clamped, continuously resonant DC link inverter, this soft-switched inverter can reduce voltage stresses from more than 2 per unit (pu) to 1.1-1.3 pu. It can also provide soft-switched pulse-width modulated (PWM) operation. Simulations and experiments are performed to backup the analysis     

一种用于MEMS加速度传感器的低功耗低噪声全差分电路

设计了一种用于MEMS加速度传感器的低功耗低噪声的全差分电路,采用套筒式电路结构,增加了输出阻抗,减少了功耗和噪声。适当的共模反馈,提高了环路足够的补偿,避免了输出信号的失真,确保获得好的相位裕度以及一个快速的反应。在0.5μm CMOS工艺模型下,Cadence Spectre电路仿真的结果表明,电源电压为5 V,频率的范围是0.1 Hz到100 MHz时,得到电路的噪声大小是5.777 891μV·Hz~(–1/2),功耗大小为41.768 m W,版图的面积为1834.18μm×1446.87μm。这一电路可以用于地震监测以及石油勘探等领域。     

A soft-switched, high-frequency resonant rectifier andcharacteristics of the controlled system

In this paper, a high frequency and soft-switched AC/DC rectifier employing a series-type resonant circuit is proposed to obtain the sinusoidal AC line current. Using the proposed rectifier, the high power factor and low harmonic currents are obtained in the AC line. Furthermore, several advantages such as the high power density and wide output voltage range can also be available. To regulate the output voltage of the proposed circuit, the digital proportional-integral (PI) controller is used whose sampling time corresponds to the zero-crossing point of the AC line voltage. Including this controller, the model for the closed-loop system is developed in order to examine the stability and dynamic characteristics. With this model, the gain of the PI-controller is determined by the pole assignment technique and the closed-loop dynamics is investigated by the root locus plots. A good agreement is made between the simulated and experimental results     

A very high-speed CMOS 4-2 compressor using fully differential current-mode circuit techniques

This paper presents a new high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. Current-mode techniques have been used to improve the overall performance of the compressor. New fully differential proposed circuit improves speed up to 45% also reduces occupied area in comparison to other high-speed conventional compressor circuits. To evaluate the performance of the proposed circuit, two other structures have been chosen and all of the circuits have been simulated in 0.18 μm standard TSMC CMOS process with 1.8 V power supply voltage.     

A new, soft-switched, high-power-factor boost converter with IGBTs

A new soft-switching technique that improves performance of the high-power-factor boost rectifier by reducing switching losses is introduced. The losses are reduced by an active snubber which consists of an inductor, a capacitor, a rectifier, and an auxiliary switch. Since the boost switch turns off with zero current, this technique is well suited for implementations with insulated-gate bipolar transistors. The reverse-recovery-related losses of the rectifier are also reduced by the snubber inductor which is connected in series with the boost switch and the boost rectifier. In addition, the auxiliary switch operates with zero-voltage switching. A complete design procedure and extensive performance evaluation of the proposed active snubber using a 1.2 kW high-power-factor boost rectifier operating from a 90 V_rms-256 V_rms input are also presented     

A high-efficiency soft-switched AC/DC converter with current-doubler synchronous rectification

An improved ac/dc converter based on asymmetrical half-bridge topology is proposed in this paper. To substantially enhance the efficiency for low-voltage/high-current output applications, a current-doubler synchronous rectifier is combined with a modified asymmetrical half-bridge converter that retains the inherent zero-voltage-switching property. The power losses in the secondary rectification stage and the primary switches can be significantly reduced. The proposed architecture exhibits extreme simplicity and lower cost while providing unity power factor, well-regulated output, and high power density. The detailed operating principles and design procedures for the proposed converter are described in this paper. Simulation and experimental results for a laboratory prototype are discussed to verify the feasibility.     

A new fully recessed-oxide (FUROX) field isolation technology for scaled VLSI circuit fabrication

A more reliable process for near-zero bird's beak and fully recessed field isolation structure has been developed, which effectively reduces the narrow channel width effects which exist in the conventional local oxidation of silicon (LOCOS) processing. This proposed new process mainly consists of a new nitride masking structure for a two-step field oxidation and a self-aligned field implantation. Using a thin nitridized oxide as a buffer layer underneath the oxidation mask, the bird's beak of the first field oxide is largely reduced by the nitridation-enhanced interface sealing ability. No additional masking steps are required. The MOSFET's with various channel widths have been fabricated and characterized, and comparisons between the new isolation technique and the conventional LOCOS have been made. The improvement in device performance using the proposed isolation technique in MOS/VLSI fabrication is also clearly demonstrated.