可编程逻辑器件设计新思路

可编程逻辑器件在集成电路的发展中占有重要地位。深亚微米与超深亚微米技术的发展使可编程逻辑器件向系统级可编程芯片转移。本文详细阐述了基于IP的系统级可编程芯片的设计策略。     

漫谈可编程逻辑器件

<正> 目前,通用的标准数字集成电路,如74系列、4000系列、14500系列,已广泛用于业余制作和一般产品中。这些集成电路通常都是小规模集成电路(SSI)或中规模集成电路(MSI)。 除此之外,在数字电路家族中有一类专用集成电路(ASIC)。专用集成电路,电子爱好者用得不多,主要是批量生产厂家使用。在复杂的电路系统中,往往用到许多块集成电路,使印刷电路相对复杂,占用印刷电路板面积大,可靠性下降。如果要改进电路,则需要重新设计电路板,生产厂家为了解决这一问题,可以根据自己的需要,向集成电路厂家提出要求,由集成电路厂家设计专用集成电路,然后再试制、批量生产。通常,专用集成电路的设计周期和生产     

可编程阵列逻辑器件在通信系统中的应用

近年来,可编程逻辑器件（ＰＬＤ）已广泛应用于计算机系统、数据处理、接口技术和工业控制等领域中,文中阐述了可编程阵列逻辑（ＰＡＬ）器件在差分四相多相键控（ＤＱＰＳＫ）发送端中的应用,结果表明,与中小规模集成电路设计方法相比,彩可阵列逻辑器件的设计方法不仅体积小、功耗低、可靠性高,而且安装、调试过程更为简便。     

可编程逻辑器件替代ASIC

具有很大吸引力的可编程逻辑最 新发展趋势是用以替代ＡＳＩＣ和ＡＳＳＰ（Ａｐｐｌｉｃａｔｉｏｎ Ｓｐｅｃｉｆｉｃ ＳｔａｎｄｕｒｄＰｒｏｄｕｃｔ—一专用标准产品）。过去的经验法则是：假若需要量少，则正确的选择是可编程逻辑方案；若需要量大，采用ＡＳＩＣ方案是值得的，虽然在时间和灵活性方面有所损失，但成本是合算的。 而现在，事实上已不必这样做了。Ｘｉｌｉｎｘ公司（ｗｗｗ．ｘｉｌｉｎｘ．ｃｏｍ）推出最新的可编程逻辑家族Ｓｐａｒｔａｎ－ＩＩ和ＣｏｏｌＲｕｎｎｅｒ ＸＰＬＡ３（见图 １），设计人员可用它们替代ＡＳ…     

可编程逻辑器件风光无限

可编程逻辑器件(PLD)正在当今的电子行业里扮演着愈来愈重要的角色。过去的10年来,PLD的发展速度比半导体快4倍,这是由于在通信和电子技术方面,新技术和新标准的更新频率越来越快,为了应对这日新月异的发展速度,为了降低开发成本和缩短产品面市时间,设计者无法不垂青于高灵活性和低开发成本的PLD。     

可编程逻辑器件现状及发展趋势

可编程逻辑器件现状可编程逻辑器件发展很快,已经从20年前几百门的PAL/GAL发展到现在的超过300万门的FPGA,已拥有可以提供足够系统集成容量的密度、增强的嵌入系统能力、功能集合及许多其他特性的新器件。新的开发工具提供了对这些新器件的支持,并具有以更高的生产率实现数百万门电路设计的能力。与新芯片及软件相配合的是带知识产权的系统级设计模块解决方案,它们的参数可由用户自定。芯片、软件及知识产权功能构成了完整的可编程解决方案,可编程逻辑已成为系统集成的平台。1、全球可编程逻辑器件市场现状根据IDC的数据,可编程…     

可编程通用阵列逻辑器件应用技术讲座

本讲座通过介绍专用集成电路(ASIC)入手,介绍了可编程逻辑器件的原理和结构,从应用的角度介绍通用逻辑器件(GAL)的结构和特点,以及有关PLD的编程技术,最后给出几个实用的编程实例和GAL器件的应用电路.     

可编程阵列逻辑器件在通信系统中的应用

近年来，可编程逻辑器件（ＰＬＤ）已广泛用于计算机系统，数据处理，接口技术和工业控制等领域中，本文阐述了可编程阵列逻辑（ＰＡＬ）器件在差分四相移相键控（ＤＱＰＳＫ）发送端中的应用，结果表明，与中小规模集成电路设计中方法相比，采用可编程阵列逻辑器件的设计方法不仅体积小，功耗低，可靠性高，而且安装，调试过程更为简便。     

系统级可编程芯片(SOPC)设计思想与开发策略

针对SOPC全新的设计流程，提出了基于IP的SOPC设计集成平台概念及设计思想与开发策略，并介绍了基于FPGA／CPLD的SOPC的实现方案。     

片上网络:新一代的片上系统结构

片上系统是使用共享或专用总线作为芯片的通信资源.由于这些总线具有一定的限制,因此扩展性较差,不能满足发展需求.在这种情况下,目前的片内互连结构将成为多核芯片的发展瓶颈.文章介绍了一种新型的片上体系结构(片上网络)来解决未来片上系统中总线所带来的不足.片上网络作为一种新的片上体系结构,可以解决片上系统设计中所带来的各种挑...     

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little smart logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.Jeffrey Draper is a Research Assistant Professor in the Department of Electrical Engineering at the University of Southern California. He holds this appointment in conjunction with a Project Leader position at the Information Sciences Institute of the University of Southern California. Dr. Drapers research group has participated in many DARPA-sponsored large-scale VLSI development efforts. He is a member of the IEEE Computer Society and has conducted research in the areas of processing-in-memory architectures, thermal management, VLSI, interconnection networks, and modeling/performance evaluation. Dr. Draper received a BSEE from Texas A&M University and an MS and PhD from the University of Texas at Austin.J. Tim Barrett is a Senior Electrical Engineer at the Information Sciences Institute of the University of Southern California. Mr. Barrett has managed, designed and implemented the hardware, low-level software and integration of many computer systems. Applications of these systems include scalable supercomputers at USC Information Sciences Institute, the long distance telephone switch at AT&T Bell Labs, building energy management at Barber-Colman Company, and laser entertainment performance instruments at Aura Technologies and Laser Images Inc. He is a member of IEEE Solid State Circuits Society and received his MSCS from the University of Illinois Chicago and BSEE from the University of Iowa.Jeff Sondeen is a Research Associate at the Information Sciences Institute of the University of Southern California, where he supports and maintains CAD technology files, libraries, and tools for implementing VLSI designs. Previously he has worked at Silicon Compilers and Hewlett-Packard in CAD tool and test chip development. He received an MSEE from the University of Michigan.Sumit Mediratta is currently pursuing a PhD in Electrical Engineering at the University of Southern California. He received a Bachelor of Engineering degree in Electronics and Telecommunication from the Shri Govind Ram Sekseria Institute of Technology and Science, India. His research interests include interconnection networks, VLSI, processing-in-memory architectures, high-speed data communication and synchronization techniques and network interfaces for high-performance architectures.Chang Woo Kang received a BS in electrical engineering from Chung-ang University, Seoul, South Korea, in 1997 and an MS in electrical engineering from the University of Southern California, Los Angeles, in 1999. He is currently pursuing a PhD in electrical engineering at the University of Southern California. His research includes VLSI system design and algorithms for low-power logic synthesis and physical design.Ihn Kim is a PhD student in the Department of Electrical Engineering at the University of Southern California. He is also a Staff Engineer at QLogic. His research interests include user-level network interface, network processor architectures, and modeling/performance evaluation of system area networks. He is a member of the IEEE Computer Society. He received an MS at KAIST (Korea Advanced Institute of Science and Technology).Gokhan Daglikoca is an Application Engineer at Cadence Design Systems, Inc, where he specializes in High-Performance ASIC and Microprocessor Design Methodologies. He is a member of IEEE. Gokhan Daglikoca received a BS from Istanbul Technical University and an MS from the University of Southern California.     

FPGA芯片时钟架构分析

FPGA设计中时钟信号的设计与处理是保证系统稳定工作的重要组成部分,随着FPGA器件规模的不断增大,集成度不断提高,多时钟域管理、时钟延迟、时钟信号完整性和相位偏移等已成为影响FPGA设计的关键因素。结合微电子电路相关知识,针对Xilinx公司的Virtex4系列芯片,详细分析其时钟架构及时钟资源的特性。针对FPGA时钟设计的典型应用情况,从芯片角度给出了时钟设计与使用的一些技巧和建议。     

基于FPGA的ASIC芯片抗辐射性能评估系统

针对航天电子控制系统对集成电路的抗辐射需求,设计了一种基于现场可编程门阵列(FPGA)的全新架构的专用集成电路(ASIC)抗辐射性能评估系统。该系统基于FPGA高性能、高速度、高灵活性和大容量的特性,不仅具备传统芯片评估系统的能力,还具备精确判定失效事件发生时刻、被测ASIC时序、内部状态及大致的内部路径位置的能力。对该系统进行单粒子翻转(SEU)辐射试验,试验结果表明,在81.4 MeV·cm²·mg^-1的线性能量转移阈值下,该系统能自动判别没有发生SEU事件。目前,该系统已成功应用于自研高可靠性ASIC芯片抗辐射性能的评估。     

一种实现大型报文交换设备的新体系结构

简单回顾了ATM交换机、帧中继交换机和IP路由器等报文交换设备的发展历史，指出在网络带宽需求不断增加的背景下，大型报文交换设备面临的问题，介绍了一种可行的解决方案——一种新的报文交换设备体系结构。     

利用FPGA芯片实现PWM电源

为了解决模拟汽车电磁阀的工作状态设计了一种对基于FPGA的PWM电源,该测试电源在硬件上以单片机作为控制核心,控制FPGA芯输出所需的PWM波形,通过软件模块化的方式实现了测试电源输出的电压幅度、频率和占空比在指定时间范围内可按周期连续变化的功能。实践证明：该电源很好地满足了不同种类电磁阀实际工作状态的模拟需求。     

基于单片FPGA的雷达动目标检测系统

介绍了一种基于单片现场可编程门阵列（FPGA）的雷达动目标检测系统,阐述了恒虚警处理和FPGA技术,对输入数据的存取方式、多普勒滤波器组和恒虚警处理的实现进行了详细论述。     

利用现场可编程门阵列FPGA开发专用实时图像处理系统芯片

本文介绍了一个实时图像处理系统中，利用ＦＰＧＡ开发专用算法模块的范例，使人 ＦＰＧＡ的应用方法有一个较完整的认识。     

基于FPGA的芯片功能性验证自动化实现

针对传统半导体设计流程中对MCU芯片进行功能性验证时涉及到多个芯片之间的互联,手工操作连接十分烦琐且易出现错误,介绍了一种基于FPGA的MCU引脚自动互联的设计与实现.介绍了MCU模块功能性验证自动化实现的概念,从硬件逻辑角度给出了一种解决方法,并且从FPGA模块设计、功能仿真和系统实现等方面,证明了新的测试方法不但降低了人为操作错误的可能性,而且提高了模块功能验证的覆盖率和验证效率,大大缩短了产品的上市时间.     

板载FPGA芯片的边界扫描测试设计

边界扫描技术是标准化的可测试性设计技术，它提供了埘电路板上器件的功能、互连及相互问影响进行测试的一类方法，极大地方便了对于复杂电路的测试。文中针对某设备分机具体的待测电路，遵循IEEE1149.1标准，结合FPGA芯片的BSDL文件进行边界扫描测试设计，理解和掌握其设计原理、数据结构，并实现板级测试与ATE的接口。