NTRU公开密钥体制及其应用

公开密钥体制NTRU算法的安全性取决于从一个非常大的维数格中寻找很短向量的困难性上,它高速、低需求、易实现、密钥产生容易.介绍了这种密钥体制的理论基础和使用方法并与其它密码体系进行了比较.     

NTRU公开密钥体制快速实现算法

NTRU算法是一种基于环的公开密钥体制,与RSA和ECC等典型的加密算法相比,在安全性和速度方面具有明显的优势.分析了目前NTRU算法的研究状况,提出了具体、完整和快速实现NTRU公开密钥体制的方法,包括产生随机多项式、卷积计算和模p计算算法.给出的方法适用与NTRU-1998、NTRU-2001和NTRU-2005.可以提高NTRU算法的速度达50%以上.     

数论变换在异步保密机中的应用

本文讨论了数论变换在异步保密系统中的应用。首先对数论变换应用后系统所出现的问题进行了描述,然后分析,讨论了这些问题产生的原因,并针对输入信号动态范围的扩展,数论变换非线性控制等提出了相应的解决方法,这些方法在实践中得到了证明     

MC—隐线性变换型公钥密码体制

本文将MC(Matrix Cover)问题与线性变换相结合,提出了一种新型公钥密码体制。新体制的安全性主要依赖于MC的NP-完全性问题。     

公钥密码Naccache-Stern的安全性分析

该文对Naccache-Stern公钥密码体制进行了安全性分析,给出了一种攻击方法。其基本思想是,把解密看作一个群分解问题,求解该问题即可获得一个等价明文。当该等价明文向量的各个分量都很小时,则此等价明文就是密文所对应的明文。该攻击算法攻击成功的概率大于直接求解离散对数问题。该算法攻击成功的概率依赖于把一个随机的自然数转化成一个光滑数的概率。     

基于Niederreiter纠错码的公钥密码体制的研究

二十多年来,纠错码成功地用于构造诸多纠错码公钥密码体制。文中首先研究了N公钥体制的性能指标,给出了它的计算机模拟曲线;通过分析N公钥体制的安全性,给出了一种攻击N公钥体制的新方法;然后探讨M公钥体制与N公钥体制的内在关系,揭示了它们之间安全性等价的事实,给出了M公钥与N公钥体制性能比较的结果。     

应用于格密码的可重构多通道数论变换硬件设计

针对不同格密码体制带来的数论变换参数多样性,以及数论变换的性能优化设计,该文提出一种基于随机存取存储器(RAM)的可重构多通道数论变换单元。在数论变换单元设计中,在按时间抽取的基础上改进多通道架构,并提出一种优化地址分配方法。最后基于Xilinx Artix-7现场可编程逻辑门阵列(FPGA)平台进行原型实现,结果显示,所设计的数论变换单元消耗的资源为1744 Slices, 16 DSP,完成1次多项式乘法的时间为2.01 μs(n=256), 3.57 μs(n=512), 6.71 μs(n=1024)和13.43 μs(n=2048),支持256～2048的不同参数n和13～32 bit模q的可重构配置,工作频率最高可达232 MHz。     

基于圆周卷积的长序列小波变换快速实现

根据小波变换的基本特点,在运用重叠保留法对长序列进行分段处理的基础上,提出用圆周卷积来实现快速小波变换中大量的线性卷积运算。通过Matlab仿真实现,结果验证了算法的正确性,运算速度较传统线性卷积方法有很大提高。该方法有着很好的并行度,有利于信号的实时处删。     

Hardware Efficient Fast Computation of the Discrete Fourier Transform

In this paper, a new systolic array for prime N-length DFT is first proposed, and then combined with Winograd Fourier Transform algorithm (WFTA) to control the increase of the hardware cost when the transform length is large. The proposed new DFT design is both fast and hardware efficient. Compared with the recently reported DFT design with computational complexity of O(log N), the proposed design saves the average number of required multiplications by 30 to 60% and reduces the average computation time by more than 2 times, when the transform length changes from 16 to 2048. Chao Cheng received his MSEE degree from Huazhong University of Science and Technology, Wuhan, China, in 2001. With three years industrial experience as a digital communication engineer from VIA Technologies, he is now pursuing his Ph.D. degree at the University of Minnesota, Twin Cities, MN. His present research interest is in VLSI digital signal processing algorithms and their implementation. Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, and ultra wideband systems. He has published over 400 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and Signal Processing Magazine, and currently serves as the Editor-in-Chief of the IEEE Trans. on Circuits and Systems---I (2004--2005 term), and serves on the Editorial Board of the Journal of VLSI Signal Processing. He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996--1998. He is a Fellow of IEEE (1996). An erratum to this article is available at .     

一种长序列小波变换快速算法的DSP实现

由于小波变换算法的复杂性,直接计算小波变换耗时较长,微机和通用的微处理器在运算速度上难以实现小波变换的实时性要求.定点DSP具有低功耗、高性能的特点,本文结合TI公司的16位定点DSP,将小波变换快速算法用C语言开发,详细说明了小波变换快速算法在定点DSP上的具体实现,解决了小波变换实时、高精度处理的要求,大大提高了小波变换的运算效率.