Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown(TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy(SIMS) analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio N_(it)/N_(ot) are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo(kMC) method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.     

AlGaN barrier thickness dependent surface and interface trapping characteristics of AlGaN/GaN heterostructure

The aluminium gallium nitride (AlGaN) barrier thickness dependent trapping characteristic of AlGaN/GaN heterostructure is investigated in detail by frequency dependent conductance measurements. The conductance measurementsin the depletion region biases (−4.8 V to −3.2 V) shows that the Al_0.3Ga_0.7N(18 nm)/GaN structure suffers from both the surface (the metal/AlGaN interface of the gate region) and interface (the AlGaN/GaN interface of the channel region) trapping states, whereas the AlGaN/GaN structure with a thicker AlGaN barrier (25 nm) layer suffers from only interface (the channel region of AlGaN/GaN) trap energy states in the bias region (−6 V to −4.2). The two extracted time constants of the trap levels are (2.6–4.59) μs (surface) and (113.4–33.8) μs (interface) for the Al_0.3Ga_0.7N(18 nm)/GaN structure in the depletion region of biases (−4.8 V to −3.2 V), whereas the Al_0.3Ga_0.7N (25 nm)/GaN structure yields only interface trap states with time constants of (86.8–33.3) μs in the voltage bias range of −6.0 V to −4.2 V. The extracted surface trapping time constants are found to be very muchless in the Al_0.3Ga_0.7N(18 nm)/GaN heterostructure compared to that of the interface trap states. The higher electric field formation across the AlGaN barrier causes de-trapping of the surface trapped electron through a tunnelling process for the Al_0.3Ga_0.7N(18 nm)/GaN structure, and hence the time constants of the surface trap are less.     

Energy distribution extraction of negative charges responsible for positive bias temperature instability

A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability(PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 e V above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.     

高线性度Al_xGa_(1-x)N/Al_yGa_(1-y)N/GaN高电子迁移率晶体管优化设计

对新型复合沟道AlxGa1-xN/AlyGa1-yN/GaN高电子迁移率晶体管(HEMT)进行了优化设计.从半导体能带理论与量子阱理论出发,自洽求解了器件层结构参数对器件导带能级以及二维电子气(2DEG)中载流子浓度和横向电场的影响.用TCAD软件仿真得到了器件的层结构参数对器件性能的影响.结合理论分析和仿真结果确定了器件的最佳外延层结构Al0.31Ga0.69N/Al0.04Ga0.96N/GaNHEMT.对栅长1μm,栅宽100μm的器件仿真表明,器件的最大跨导为300mS/mm,且在栅极电压-2—1V的宽范围内跨导变化很小,表明器件具有较好的线性度;器件的最大电流密度为1300mA/mm,特征频率为11.5GHz,最大振荡频率为32.5GHz.     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

Structural and electrical properties of a high-k SmAlO3 charge trapping flash memory

In this study, we proposed the Al/Al₂O₃/SmAlO₃/SiO₂/Si flash memory devices using high-k SmAlO₃ film as a charge trapping layer and high-k Al₂O₃ film as a blocking layer. The structural and morphological features of these films were explored by X-ray diffraction, X-ray photoelectron spectroscopic and atomic force microscopy. The SmAlO₃ flash memory devices annealed at 800 °C showed excellent electrical properties, such as a large memory window of ～2.61 V (measured at a sweep voltage range of ±5 V) and a small charge loss of ～7.1% (measured time up to 10⁴ s). In addition, the charge trap centroid and charge trap density were extracted by constant current stress method.     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

钛－镍－硅固相反应形成的镍硅化物/n-硅(100)接触的I-V-T研究

在不同退火温度下，有一薄层钛覆盖层的镍－硅经过固相反应生成了镍硅化物/n-硅(100)接触，研究了其在80K到室温的电流－电压（I-V）特性。低温I-V曲线在低偏压区的电流显著地比传统的热电子发射（TE）模型预计的要大。用基于Tung的夹断模型简化得到的双肖特基势垒模型分析了实测的I-V曲线，从中可以得到肖特基势垒不均匀性的量度。较高温度退火导致较大的势垒不均匀性，意味着硅化物薄膜均匀性的变坏。钛覆盖薄层可以稍微提高硅化镍的相转变温度，以及形成的一硅化镍的热稳定性。     

Normal-incidence reflectance of optimized W /B(4) C x-ray multilayers in the range 1.4 nm < l > 2.4 nm

We have fabricated W/B(4)C multilayers having periods in the range d = 0.8-1.2 nm and measured their soft-x-ray performance near normal incidence in the wavelength range 1.4相似文献   

N2O Plasma表面处理对SiNx基IGZO-TFT性能的影响

采用N₂O plasma处理SiN_x薄膜作为绝缘层,以室温下沉积的铟镓锌氧化物(IGZO)作为有源层制备了 IGZO薄膜晶体管。与常规的IGZO-TFT相比,N₂O plasma处理过的IGZO-TFT的迁移率由原来的4.5 cm²·V^-1·s^-1增 加至8.1 cm²·V^-1·s^-1,阈值电压由原来的11.5 V减小至3.2 V,亚阈值摆由原来的1.25 V/decade减小至0.9 V/decade。采用C-V方法计算了两种器件的陷阱态,结果发现N₂O plasma处理过的IGZO-TFT的陷阱态明显小于普通的IGZO-TFT的陷阱态,表明N₂O plasma处理SiN_x绝缘层是一种改善IGZO-TFT器件性能的有效方法。     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

Swift ion irradiation effect on high-k ZrO2- and Al2O3-based MOS devices

This paper describes the heavy ion-induced effects on the electrical characteristics of reactively sputtered ZrO₂ and Al₂O₃ high-k gate oxides deposited in argon plus nitrogen containing plasma. Radiation-induced degradation of sputtered high-k dielectric ZrO₂/Si and Al₂O₃/Si interface was studied using 45?MeV Li³⁺ ions. The devices were irradiated with Li³⁺ ions at various fluences ranging from 5?×?10⁹ to 5?×?10¹²?ions/cm². Capacitance–voltage and current–voltage characteristics were used for electrical characterization. Shift in flat band voltage towards negative value was observed in devices after exposure to ion radiation. Post-deposition annealing effect on the electrical behavior of high-k/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, interface defect density and oxide-trapped charge have been extracted.The surface morphology and roughness values for films deposited in nitrogen containing plasma before and after ion radiation are extracted from Atomic Force Microscopy.     

SeX(X=H,C,N,O)的结构与势能函数

用密度泛函B3LYP方法对SeX(X=H,C,N,O) 分子体系进行了理论研究,得到SeX(X=H,C,N,O) 分子体系的基态电子状态的平衡几何Re和离解能De,并在计算出来的一系列单点势能基础上,用正规方程组拟合Murrell-Sorbie(M-S)势能函数,得到相应态的解析势能函数,光谱参数Be、αe、ωe、和ωeχe为:HSe:7.74786cm-1、0.22000cm-1、2425.33344cm-1 and 39.51563cm-1;SeC:0.56678cm-1、0.00370cm-1、1021.70315cm-1、5.10000cm-1;NSe:0.45528cm-1、0.00375cm-1、946.30895cm-1、4.98923cm-1;OSe:0.45296cm-1、0.00001cm-1、889.77025cm-1、4.55983cm-1.由此计算对应的光谱参数和力学性质.结果表明SeX(X=H,C,N,O) 分子体系是可稳定存在的.     

The electronic and chemical structure of the a-B(3)CO(0.5):H(y)-to-metal interface from photoemission spectroscopy: implications for Schottky barrier heights

The electronic and chemical structure of the metal-to-semiconductor interface was studied by photoemission spectroscopy for evaporated Cr, Ti, Al and Cu overlayers on sputter-cleaned as-deposited and thermally treated thin films of amorphous hydrogenated boron carbide (a-B(x)C:H(y)) grown by plasma-enhanced chemical vapor deposition. The films were found to contain ～10% oxygen in the bulk and to have approximate bulk stoichiometries of a-B(3)CO(0.5):H(y). Measured work functions of 4.7/4.5?eV and valence band maxima to Fermi level energy gaps of 0.80/0.66?eV for the films (as-deposited/thermally treated) led to predicted Schottky barrier heights of 1.0/0.7?eV for Cr, 1.2/0.9?eV for Ti, 1.2/0.9?eV for Al, and 0.9/0.6?eV for Cu. The Cr interface was found to contain a thick partial metal oxide layer, dominated by the wide-bandgap semiconductor Cr(2)O(3), expected to lead to an increased Schottky barrier at the junction and the formation of a space-charge region in the a-B(3)CO(0.5):H (y) layer. Analysis of the Ti interface revealed a thick layer of metal oxide, comprising metallic TiO and Ti (2)O (3), expected to decrease the barrier height. A thinner, insulating Al(2)O(3) layer was observed at the Al-to-a-B(3)CO(0.5):H(y) interface, expected to lead to tunnel junction behavior. Finally, no metal oxides or other new chemical species were evident at the Cu-to-a-B(3)CO(0.5):H(y) interface in either the core level or valence band photoemission spectra, wherein characteristic metallic Cu features were observed at very thin overlayer coverages. These results highlight the importance of thin-film bulk oxygen content on the metal-to-semiconductor junction character as well as the use of Cu as a potential Ohmic contact material for amorphous hydrogenated boron carbide semiconductor devices such as high-efficiency direct-conversion solid-state neutron detectors.     

A quantitative analysis of a multi-phase polycrystalline cubic boron nitride tool material using DualEELS

This paper presents a quantitative analysis of a polycrystalline cubic boron nitride tool material by electron energy-loss spectroscopy spectrum imaging acquired in dual range mode. Having both the low-loss and core-loss regions acquired nearly simultaneously provides the advantage of accurate corrections for thickness effects and thus the possibility to perform quantification calculations. This has resulted in extracted bonding maps with areal (atoms/nm(2)) or volumetric (atoms/nm(3)) densities. Spectroscopic signatures in the low-loss and core-loss energy ranges, of the elements (Al, B, C, N, Ti and O) present in the existing phases, were studied and used when extracting the element specific bonding maps by the multiple linear least squares fitting procedure. Variations of elemental concentrations across the investigated area were determined, despite of phase overlap in the beam direction or energy overlaps in the EELS spectrum. Moreover, the surface oxidation of Ti(C,N) and AlN as well as the amorphisation of α-Al(2)O(3) is discussed.     

Effect of tin-doped indium oxide film as capping layer on the agglomeration of copper film and the appearance of copper silicide

In this work, the effect of tin-doped indium oxide (ITO) film as capping layer on the agglomeration of copper film and the appearance of copper silicide was studied. Both samples of Cu 100 nm/ITO 10 nm/Si and ITO 20 nm/Cu 100 nm/ITO 10 nm/Si were prepared by sputtering deposition. After annealing in a rapid thermal annealing (RTA) furnace at various temperatures for 5 min in vacuum, the samples were characterized by four probe measurement for sheet resistance, X-ray diffraction (XRD) analysis for phase identification, scanning electron microscopy (SEM) for surface morphology and transmission electron microscopy (TEM) for microstructure.The results show that the sample with ITO capping layer is a good diffusion barrier between copper and silicon at least up to 750 °C, which is 100 °C higher than that of the sample without ITO capping layer. The failure temperature of the sample with ITO capping layer is about 800 °C, which is 100 °C higher than that of the sample without ITO capping layer. The ITO capping layer on Cu/ITO/Si can obstacle the agglomeration of copper film and the appearance of Cu₃Si phase.