High holding voltage SCR for robust electrostatic discharge protection

A novel silicon controlled rectifier(SCR) with high holding voltage(Vh) for electrostatic discharge(ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N+ layer(LN+) and a long P+ layer(LP+), which divide the conventional low voltage trigger silicon controlled rectifier(LVTSCR) into two SCRs(SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current(IESD), the two SCRs are turned on at the same time to induce the first snapback with high V_h(V_(h1)). As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h(V_(h2)). The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like(Transmission Line Pulse-like) simulation. An optimized V_(h2) of 7.4 V with a maximum failure current(I_(t2)) of 14.7 m A/μm is obtained by the simulation.     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

传输线长度对静电放电防护器件性能测试的影响

为了研究传输线长度对静电放电防护器件性能测试结果的影响,建立了静电放电模型和传输线脉冲模型两种试验系统,对某限压型防护器件进行了快沿电磁脉冲注入试验,并进行了理论分析。结果表明:传输线长度对静电放电防护器件性能测试结果具有极大影响,选用不当会导致错误结论;在对静电放电防护器件性能测试时,应优先采用传输线脉冲测试法;当采用静电放电脉冲测试法时,其传输线长度不应小于8 m。     

隧道场效应晶体管静电放电冲击特性研究

随着器件尺寸的不断减小,集成度的逐步提高,功耗成为了制约集成电路产业界发展的主要问题之一.由于通过引入带带隧穿机理可以实现更小的亚阈值斜率,隧道场效应晶体管(TFET)器件已成为下一代集成电路的最具竞争力的备选器件之一.但是TFET器件更薄的栅氧化层、更短的沟道长度容易使器件局部产生高的电流密度、电场密度和热量,使得其更容易遭受静电放电(ESD)冲击损伤.此外,TFET器件基于带带隧穿机理的全新工作原理也使得其ESD保护设计面临更多挑战.本文采用传输线脉冲的ESD测试方法深入分析了基本TFET器件在ESD冲击下器件开启、维持、泄放和击穿等过程的电流特性和工作机理.在此基础之上,给出了一种改进型TFET抗ESD冲击器件,通过在源端增加N型高掺杂区,有效的调节接触势垒形状,降低隧穿结的宽度,从而获得更好的ESD设计窗口.     

环栅肖特基势垒金属氧化物半导体场效应管漏致势垒降低效应研究

结合环栅肖特基势垒金属氧化物半导体场效应管(MOSFET)结构, 通过求解圆柱坐标系下的二维泊松方程得到了表面势分布, 并据此建立了适用于低漏电压下的环栅肖特基势垒NMOSFET阈值电压模型.根据计算结果, 分析了漏电压、沟道半径和沟道长度对阈值电压和漏致势垒降低的影响, 对环栅肖特基势垒MOSFET器件以及电路设计具有一定的参考价值. 关键词： 环栅肖特基势垒金属氧化物半导体场效应管 二维泊松方程 阈值电压模型 漏致势垒降低     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Ultra-high-voltage(UHV) junction field-effect transistors(JFETs) embedded separately with the lateral NPN(JFETLNPN), and the lateral and vertical NPN(JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge(ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.     

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

Trigger characteristics of electrostatic discharge(ESD) protecting devices operating under various ambient temperatures ranging from 30℃ to 195℃ are investigated.The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator(PDSOI) technology.The measurements are conducted by using a transmission line pulse(TLP) test system.The different temperature-dependent trigger characteristics of groundedgate(GGNMOS) mode and the gate-triggered(GTNMOS) mode are analyzed in detail.The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_(T1) investigated through the assist of technology computer-aided design(TCAD) simulation.     

High voltage tolerant on-chip ESD protection in low-voltage BiCMOS process

A dual-direction ESD protection approach is applied to the problem of 60 V tolerant on-chip protection of the thin film resistors in automotive application circuits realized in 5 V BiCMOS process. A novel method for increasing the breakdown voltage of a blocked N-isolation layer is proposed and validated using process and device numerical simulation followed by experimental measurements.     

ESD protection for the tolerant I/O circuits using PESD implantation

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call “PESD” implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μm process, this method provides a significant improvement in the cascode ESD performance.     

A snapback-free TOL-RC-LIGBT with vertical P-collector and N-buffer design

A reverse-conducting lateral insulated-gate bipolar transistor(RC-LIGBT) with a trench oxide layer(TOL), featuring a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surface and bulk electric fields of the N-drift region, thus the breakdown voltage(BV) is improved. Secondly, the vertical N-buffer layer increases the voltage drop VPNof the P-collector/N-buffer junction, thus the snapback is suppressed. Thirdly, the P-body and the vertical N-buffer act as the anode and the cathode, respectively, to conduct the reverse current, thus the inner diode is integrated. As shown by the simulation results, the proposed RC-LIGBT exhibits trapezoidal electric field distribution with BV of 342.4 V, which is increased by nearly 340% compared to the conventional RC-LIGBT with triangular electric fields of 100.2 V. Moreover,the snapback is eliminated by the vertical N-buffer layer design, thus the reliability of the device is improved.     

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate(DM-DG) strained Si(s-Si) metal–oxide semiconductor field effect transistors(MOSFETs) are presented. The surface potential and the surface electric field expressions have been obtained by solving Poisson's equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate(SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.     

Efficient compact model for calculating the surface potential of carbon-nanotube field-effect transistors using a curve-fitting method

This paper presents an analytical method to compute the surface potential of ballistic metal-oxide semiconductor field-effect transistor (MOSFET)-like carbon-nanotube field-effect transistors (CNFETs). The proposed compact model considers the surface potential as functions of the carbon-nanotube diameter, gate insulator thickness, gate voltage and drain voltage. One of the advantages of this model is that there is no need to refer to the numerical model to recalculate the surface potential each time nanotube diameter or insulator thickness is changed. Instead of using a constant smoothing parameter regardless of the device size and applied bias voltages, a parameter calculated for the specific situations is employed to provide the simulation results with higher accuracy. The validity of the proposed model was verified by comparing the simulated output characteristics of three CNFETs with those of the numerical model and the previous compact model.     

Enhanced ESD properties of GaN-based light-emitting diodes with various MOS capacitor designs

High electrostatic discharge (ESD) protection of GaN-based light-emitting diodes (LEDs) has been developed using a metal–oxide semiconductor (MOS) capacitor. This structure is realized by adopting various metal electrode patterns. The MOS capacitor can be implemented by extending the metal line directly from the p-type electrode to the top surface of an SiO₂-capped n-GaN layer near the vicinity of the n-type electrode. By connecting a MOS capacitor in parallel with the GaN-based LED, the negative ESD strike could be significantly increased from 385 to 1075 V of human body mode (HBM).     

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench(HK TG VDMOS) is proposed in this paper.The HK TG VDMOS features a high-k(HK) trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage(BV).Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction(SJ) vertical double-diffused metal-oxide semiconductor(VDMOS),the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS(TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).     

Design of a silicon-based field-effect electro-optic modulator with enhanced light-charge interaction

A new design for an all-silicon field-effect optical modulator in a ring resonator geometry is proposed and modeled by means of finite-element method simulations. It is shown that the optimal relative placement of the ultrathin field-effect-generated charge layers and the optical mode in the strong-confinement waveguides leads to more than an order-of-magnitude enhancement in the light-charge interaction compared with the recent predictions in the literature. We show that such an enhancement could provide optical modulation with a >7 dB extinction-ratio using a voltage swing of only 2 V, thus making our design compatible with complementary metal-oxide semiconductor technology.     

短波接收天线系统核电磁脉冲注入试验

为评估高空核电磁脉冲(HEMP)对某型短波接收天线系统的威胁,对包含浪涌保护器在内的天线前端设备进行HEMP传导注入试验。采用纳秒级快前沿方波源和双指数波电流源,分别测试不同浪涌保护措施的快脉冲响应。结果表明,主要由于天线末端的气体放电管在高过压比下很快动作(1 ns量级)、信号浪涌保护器内瞬态电压抑制器(TVS)限幅、信号传输设备内放大器饱和限幅等多重作用,注入幅度约3.5 kV的快前沿方波、电流峰值1.8 kA的双指数波(20/500 ns)脉冲都能及时泄放,只在传输设备输出端产生一个幅度饱和(< 3 V)、持续μs量级的干扰信号。对这一类低工作电压天线系统,利用基于市售浪涌保护器的多重防雷措施能够同时实现对核电磁脉冲传导环境的防护。     

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.     

漏致势垒降低效应对短沟道应变硅金属氧化物半导体场效应管阈值电压的影响

结合应变硅金属氧化物半导体场效应管(MOSFET)结构,通过求解二维泊松方程,得到了应变Si沟道的电势分布,并据此建立了短沟道应变硅NMOSFET的阈值电压模型.依据计算结果,详细分析了弛豫Si_1－βGe_β中锗组分β、沟道长度、漏电压、衬底掺杂浓度以及沟道掺杂浓度对阈值电压的影响,从而得到漏致势垒降低效应对小尺寸应变硅器件阈值电压的影响,对应变硅器件以及电路的设计具有重要的参考价值. 关键词： 应变硅金属氧化物半导体场效应管 漏致势垒降低 二维泊松方程 阈值电压模型