Electrical characteristics of MOS capacitor with HfTiON gate dielectric and HfTiSiON interlayer

The paper reports that HfTiO dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O₂ ambience, followed by an annealing in different gas ambiences of N₂, NO and NH₃ at 600℃ for 2 min. Capacitance--voltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si \equiv N bonds to passivate dangling Si bonds and replace strained Si--O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.     

Improved interface properties of an Hf02 gate dielectric GaAs MOS device by using SiNx as an interfacial passivation layer

A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance- voltage characteristic, lower leakage current density （0.785 × 10^-6 Alcm^2 at Vfo ＋ 1 V） and lower interface-state density （2.9 × 10^12 eV^-1 ·cm^-2） compared with other samples with N2- or NH3-plasma pretreatment. The influences of post- deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600 ℃ exhibits better electrical properties than that annealed at 500 ℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.     

Improved interface properties of an HfO_2 gate dielectric GaAs MOS device by using SiN_x as an interfacial passivation layer

A GaAs metal-oxide-semiconductor (MOS) capacitor with HfO2 as gate dielectric and silicon nitride (SiNx ) as the interlayer (IL) is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance-voltage characteristic, lower leakage current density (0.785 × 10-6 A/cm2 at Vfb + 1V) and lower interface-state density (2.9 × 10 12 eV-1 ·cm-2 ) compared with other samples with N2-or NH3-plasma pretreatment. The influences of post-deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600℃ exhibits better electrical properties than that annealed at 500℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.     

A GaAs MISFET with Ge3N4 gate dielectric

GaAs MIS field effect transistors with a Ge₃N₄ dielectric gate have been investigated. No hysteresis loop and drain current drift has been observed in theI _D -V _Dcharacteristics. However, performance of the devices have been found to be limited by the contact resistance. FromI _DS ^1/2 -V _G plot, the threshold voltage and effective channel mobility of the transistor have been obtained as -4.5V and 2800cm²v^–1s^–1, respectively. A maximum dc transconductance of 68 mS/mm of gate width has been achieved.     

High-k Al2O3 MOS structures with Si interface control layer formed on air-exposed GaAs and InGaAs wafers

This paper attempts to realize unpinned high-k insulator-semiconductor interfaces on air-exposed GaAs and In_0.53Ga_0.47As by using the Si interface control layer (Si ICL). Al₂O₃ was deposited by ex situ atomic layer deposition (ALD) as the high-k insulator. By applying an optimal chemical treatment using HF acid combined with subsequent thermal cleaning below 500 °C in UHV, interface bonding configurations similar to those by in situ UHV process were achieved both for GaAs and InGaAs after MBE growth of the Si ICL with no trace of residual native oxide components. As compared with the MIS structures without Si ICL, insertion of Si ICL improved the electrical interface quality, a great deal both for GaAs and InGaAs, reducing frequency dispersion of capacitance, hysteresis effects and interface state density (D_it). A minimum value of D_it of 2 × 10¹¹ eV⁻¹ cm⁻² was achieved both for GaAs and InGaAs. However, the range of bias-induced surface potential excursion within the band gap was different, making formation of electron layer by surface inversion possible in InGaAs, but not possible in GaAs. The difference was explained by the disorder induced gap state (DIGS) model.     

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.     

LaTiO高k栅介质Ge MOS电容电特性及Ti含量优化

采用共反应溅射法将Ti添加到La_2O_3中,制备了LaTiO/Ge金属-氧化物-半导体电容,并就Ti含量对器件电特性的影响进行了仔细研究.由于Ti-基氧化物具有极高的介电常数,LaTiO栅介质能够获得高k值;然而由于界面/近界面缺陷随着Ti含量的升高而增加,添加Ti使界面质量恶化,进而使栅极漏电流增大、器件可靠性降低.因此,为了在器件电特性之间实现协调,对Ti含量进行优化显得尤为重要.就所研究的Ti/La_2O_3比率而言,18.4%的Ti/La_2O_3比率最合适.该比率导致器件呈现出高k值(22.7)、低D_(it)(5.5×10~(11)eV~(-1)·cm~(-2))、可接受的J_g(V_g=1V,J_g=7.1×10~(-3)A·cm~(-2))和良好的器件可靠性.     

Effects of charge and dipole on flatband voltage in an MOS device with a Gd-doped HfO_2 dielectric

Gd-doped HfO2 has drawn worldwide interest for its interesting features.It is considered to be a suitable material for N-type metal-oxide-semiconductor(MOS)devices due to a negative flatband voltage(Vfb)shift caused by the Gd doping.In this work,an anomalous positive shift was observed when Gd was doped into HfO2.The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors,such as Fermi level pinning(FLP),a dipole at the dielectric/SiO2interface,fixed interfacial charge,and bulk charge,on Vfb.It was found that the FLP and interfacial dipole could make Vfbnegatively shifted,which is in agreement with the conventional dipole theory.The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfbshift.     

Ambipolar inverters with natural origin organic materials as gate dielectric and semiconducting layer

Thin film electronics fabricated with non‐toxic and abundant materials are enabling for emerging bioelectronic technologies. Herein complementary‐like inverters comprising transistors using 6,6′‐dichloroindigo as the semiconductor and trimethylsilyl‐cellulose (TMSC) films on anodized aluminum as bilayer dielectric layer are demonstrated. The inverters operate both in the first and third quadrant, exhibiting a maximum static gain of 22 and a noise margin of 58% at a supply voltage of 14 V. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Band diagram determination of MOS structures with different gate materials on 3C-SiC substrate

MOS capacitors were fabricated on 3C-SiC n-type substrate (001) with a 10-μm N-type epitaxial layer. An SiO₂ layer of the thickness t_OX ≈55 nm was deposited by PECVD. Circular Al, Ni, and Au gate contacts 0.7 mm in diameter were formed by ion beam sputtering and lift-off. Energy band diagrams of the MOS capacitors were determined using the photoelectric, electric, and optical measurement methods. Optical method (ellipsometry) was used to determine the gate and dielectric layer thicknesses and their optical indices: the refraction n and the extinction k coefficients. Electrical method of C = f(V_G) characteristic measurements allowed to determine the doping density ND and the flat band voltage VFB in the semiconductor. Most of the parameters which were necessary for the construction of the band diagrams and for determination of the basic physical properties of the structures (e.g. the effective contact potential difference ϕ_MS) were measured by several photoelectric methods and calculated using the measurement data. As a result, complete energy band diagrams have been determined for MOS capacitors with three different gate materials and they are demonstrated for two different gate voltages VG: for the flat-band in the semiconductor (V_G = V_FB) and for the flat-band in the dielectric (V_G = V_G0).     

Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.     

Electrical and dielectric properties of Al/HfO2/p-Si MOS device at high temperatures

The temperature dependence of capacitance–voltage (C–V) and conductance–voltage (G/w–V) characteristics of Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) device has been investigated by considering the effect of series resistance (R_s) and interface state density (N_ss) over the temperature range of 300–400 K. The C–V and G/w–V characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in MOS device. It is found that in the presence of series resistance, the forward bias C–V plots exhibits a peak, and its position shifts towards lower voltages with increasing temperature. The density of N_ss, depending on the temperature, was determined from the (C–V) and (G/w–V) data using the Hill–Coleman Method. Also, the temperature dependence of dielectric properties at different fixed frequencies over the temperature range of 300–400 K was investigated. In addition, the electric modulus formalisms were employed to understand the relaxation mechanism of the Al/HfO₂/p-Si structure.     

A study of GaN MOSFETs with atomic-layer-deposited A1203 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors （MOSFETs） with atomic-layerdeposited Al₂O₃ gate dielectrics are fabricated.The device,with atomic-layer-deposited Al₂O₃ as the gate dielectric,presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm,which are better than those reported previously with Al₂O₃ as the gate dielectric.Furthermore,the device shows negligible current collapse in a wide range of bias voltages,owing to the effective passivation of the GaN surface by the Al₂O₃ film.The gate drain breakdown voltage is found to be about 59.5 V,and in addition the channel mobility of the n-GaN layer is about 380 cm2 /Vs,which is consistent with the Hall result,and it is not degraded by atomic-layer-deposition Al₂O₃ growth and device fabrication.     

A study of GaN MOSFETs with atomic-layer-deposited Al2O3 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al₂O₃ gate dielectrics are fabricated. The device, with atomic-layer-deposited Al₂O₃ as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al₂O₃ as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the Al₂O₃ film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm²/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition Al₂O₃ growth and device fabrication.     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.     

Al2O3绝缘栅AlGaN/GaN MOS-HEMT器件温度特性研究

采用原子层淀积(ALD)实现了10 nm Al2O3为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT).通过对MOS-HEMT器件和传统MES-HEMT器件室温特性的对比,验证了新型MOS-HEMT器件饱和电流和泄漏电流的优势.通过分析MOS-HEMT器件在30-180℃之间特性的变化规律,与国内报道的传统MES-HEMT器件随温度退化程度对比,得出了器件饱和电流和跨导的退化主要是由于输运特性退化造成的,证明栅介质减小了引入AlGaN界面的表面态是提高特性的重要原因.     

Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance

Two critical aspects of the MOS scaling towards sub-100 nm gate length are addressed: the gate tunneling and capacitance modeling, and optimization of shallow source/drain (S/D) extension junction to minimize the series resistance. Both advanced physics (quantum mechanics or QM) and practical solution (circuit simulation) are used to tackle the modeling approach. Good results have been obtained compared to available experimental data, validating the hierarchical methodology used in this paper. A hybrid, semi-analytical QM model for channel carrier profile and an accurate direct tunneling model have been developed. An nMOS transistor with effective channel length of 0.08 micron has been analyzed to demonstrate the methodology proposed.     

Microstructure and dielectric properties of La2O3 doped amorphous SiO2 films as gate dielectric material

As a potential gate dielectric material, the La₂O₃ doped SiO₂ (LSO, the mole ratio is about 1:5) films were fabricated on n-Si (0 0 1) substrates by using pulsed laser deposition technique. By virtue of several measurements, the microstructure and electrical properties of the LSO films were characterized. The LSO films keep the amorphous state up to a high annealing temperature of 800 °C. From HRTEM and XPS results, these La atoms of the LSO films do not react with silicon substrate to form any La-compound at interfacial layer. However, these O atoms of the LSO films diffuse from the film toward the silicon substrate so as to form a SiO₂ interfacial layer. The thickness of SiO₂ layer is only about two atomic layers. A possible explanation for interfacial reaction has been proposed. The scanning electron microscope image shows the surface of the amorphous LSO film very flat. The LSO film shows a dielectric constant of 12.8 at 1 MHz. For the LSO film with thickness of 3 nm, a small equivalent oxide thickness of 1.2 nm is obtained. The leakage current density of the LSO film is 1.54 × 10⁻⁴ A/cm² at a gate bias voltage of 1 V.