Ferroelectric effect and equivalent polarization charge model of PbZr_(0.2)Ti_(0.8)O_3 on AlGaN/GaN MIS-HEMT

PbZr_(0.2)Ti_(0.8)O_3(PZT) gate insulator with the thickness of 30 nm is grown by pulsed laser deposition(PLD) in AlGa N/Ga N metal–insulator–semiconductor high electron mobility transistors(MIS-HEMTs). The ferroelectric effect of PZT Al Ga N/Ga N MIS-HEMT is demonstrated. The polarization charge in PZT varies with different gate voltages. The equivalent polarization charge model(EPCM) is proposed for calculating the polarization charge and the concentration of two-dimensional electron gas(2 DEG). The threshold voltage(Vth) and output current density(IDS) can also be obtained by the EPCM. The theoretical values are in good agreement with the experimental results and the model can provide a guide for the design of the PZT MIS-HEMT. The polarization charges of PZT can be modulated by different gate-voltage stresses and the Vthhas a regulation range of 4.0 V. The polarization charge changes after the stress of gate voltage for several seconds. When the gate voltage is stable or changes at high frequency, the output characteristics and the current collapse of the device remain stable.     

Structural characterization of Mg substituted on A/B sites in $$\hbox {NiFe}_2\hbox {O}_4$$ nanoparticles using autocombustion method

A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al_0.25Ga_0.75N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance–voltage (CV) characteristics. Similarly, the predicted threshold voltage (V _T) is analysed by varying barrier thickness and oxide thickness. The positive V _T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model.     

高场应力及栅应力下AlGaN/GaN HEMT器件退化研究

采用不同的高场应力和栅应力对AlGaN/GaN HEMT器件进行直流应力测试,实验发现：应力后器件主要参数如饱和漏电流,跨导峰值和阈值电压等均发生了明显退化,而且这些退化还是可以完全恢复的;高场应力下,器件特性的退化随高场应力偏置电压的增加和应力时间的累积而增大;对于不同的栅应力,相对来说,脉冲栅应力和开态栅应力下器件特性的退化比关态栅应力下的退化大.对不同应力前后器件饱和漏电流,跨导峰值和阈值电压的分析表明,AlGaN势垒层陷阱俘获沟道热电子以及栅极电子在栅漏间电场的作用下填充虚栅中的表面态是这些不同应 关键词： AlGaN/GaN HEMT器件 表面态(虚栅) 势垒层陷阱 应力     

Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high-<Emphasis Type="Italic">K</Emphasis> gate dielectric impacts on the inversion charge density

The comparison of the inversion electron density between a nanometer metal-oxide-semiconductor (MOS) device with high-K gate dielectric and a SiO₂ MOS device with the same equivalent oxide thickness has been discussed. A fully self-consistent solution of the coupled Schr?dinger–Poisson equations demonstrates that a larger dielectric-constant mismatch between the gate dielectric and silicon substrate can reduce electron density in the channel of a MOS device under inversion bias. Such a reduction in inversion electron density of the channel will increase with increase in gate voltage. A reduction in the charge density implies a reduction in the inversion electron density in the channel of a MOS device. It also implies that a larger dielectric constant of the gate dielectric might result in a reduction in the source–drain current and the gate leakage current.     

0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Q_bd)和击穿电压(Voltage to Breakdown, V_bd). 研究结果表明，低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小，而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大，击穿电压测试值也发现与击穿电量 关键词： 薄氧 可靠性 击穿电压 击穿电量     

薄栅氧化层经时击穿的参数表征研究

在恒压应力条件下测试了薄栅氧化层的击穿特性,研究了TDDB的击穿机理,讨论了栅氧化层面积对击穿特性的影响.对击穿电荷Q_BD进行了实验测试和分析,结果表明：击穿电荷Q_BD不是常数,它依赖栅氧化层面积和栅电压.对相关系数进行了拟合,给出了Q_BD的解析表达式. 关键词：     

部分耗尽结构绝缘体上硅器件的低频噪声特性

针对部分耗尽结构绝缘体上硅(silicon-on-insulator, SOI)器件低频噪声特性展开实验与理论研究. 实验结果表明, 器件低频噪声主要来源于SiO₂-Si界面附近缺陷态对载流子的俘获与释放过程; 基于此理论可提取前栅和背栅氧化层界面附近缺陷态密度分别为8×10¹⁷ eV^-1·cm^-3和2.76×10¹⁷ eV^-1·cm^-3. 基于电荷隧穿机理, 在考虑隧穿削弱因子、隧穿距离与时间常数之间关系的基础上, 提取了前、背栅氧化层内缺陷态密度随空间的分布情况. 此外, SOI器件沟道电流归一化噪声功率谱密度随沟道长度的增加而线性减小, 这表明器件低频噪声主要来源于沟道的闪烁噪声. 最后, 基于电荷耦合效应, 分析了背栅电压对前栅阈值电压、沟道电流以及沟道电流噪声功率谱密度的影响.     

基于半导体断路开关的8 MW,10 kHz脉冲发生器

 功率器件半导体断路开关具有高重复频率工作能力。采用高速绝缘栅双极晶体管组件作为初级充电回路的主开关,建立了一台工作频率为10 kHz的脉冲发生器。脉冲发生器采用磁饱和脉冲变压器、磁开关及高压脉冲电容器组等固态器件进行两级脉冲压缩,产生小于100 ns的电流脉冲,对半导体断路开关进行泵浦,半导体断路开关反向截断泵浦电流在负载上产生高压脉冲输出。实验装置在电阻负载上得到了脉冲输出功率约为8.6 MW,脉冲宽度约10 ns,重复频率10 kHz的高压脉冲输出。     

半浮栅晶体管Marx方波脉冲电源设计

为得到工业需要的大电流高重频方波脉冲,分析并改进了半导体全控型Marx发生器,在充电的同时实现了截尾功能。设计采用新型半浮栅结构晶体管 (SFGT)作为主开关,可产生kV高压、百A大电流、高重频的方波脉冲。优化了电路结构,解决直流充电源受脉冲电源放电电压冲击问题。研制得到电流100 A、频率4 kHz、脉宽4 s、负高压6 kV、上升沿下降沿均在80 ns内的方波脉冲发生器。研究了相应的SFGT磁芯隔离驱动电路,结合了SFGT栅极并联自主电容隔离驱动和IR2110的半桥驱动电路,并对半桥上的MOS管的栅极等效电路进行了理论分析,驱动电路具有抗干扰能力强且脉宽调节范围大的特点。     

MoTe2 on ferroelectric single-crystal substrate in the dual-gate field-effect transistor operation

An exfoliated MoTe₂ flake in contact with a ferroelectric single-crystal substrate was studied to examine its charge carrier modulation by neighboring ferroelectric polarization. A MoTe₂ field-effect transistor was fabricated, having a hexagonal-BN (hBN) flake and a ferroelectric substrate employed as top and bottom gate dielectrics. In the dual-gate operation, the charge conduction exhibited an ambipolar behavior with large hysteresis during the gate voltage sweep. It mainly originates from the ferroelectric nature in combination with the charge trap phenomena at the interfaces. Interestingly, we found out that holes are more easily trapped than electrons, and charge carriers in MoTe₂ are easily modulated through the top hBN gate when the electron conduction is predominantly set by the bottom ferroelectric field. However, the controllability becomes much weaker under opposing ferroelectric polarizations. This unbalanced controllability reveals the interfacial hole-trap effect resulting from ferroelectric polarization.     

Current enhancement with alternating gate voltage in the Coulomb-blockade regime of a single-wall carbon nanotube

We investigated the current–voltage characteristics of a carbon nanotube in a single electron transistor structure with alternating gate voltage. A continuous current enhancement effect with increasing frequency of the applied gate voltage up to 13 MHz is reported. Assuming that I=nef, more than 1000 electrons are driven to flow across the source–drain channel at V_DS=100 mV, 13 MHz of gate voltage (V_p-p=2 V) and T=1.8 K. The continuous current enhancement is explained by the broadening effect of the discrete energy levels of the finite-length carbon nanotube. PACS 61.46.+w; 73.23.Hk; 73.63.Fg; 81.07.De; 85.35.Kt     

Plasma immersion ion implantation with dielectric substrates

Plasma immersion ion implantation (PIII) is a novel implantation technique for high-dose/high-current implants. Using the SPICE circuit simulator to model the PIII process, the sheath voltage and ion energy distribution are examined. Implanting into a dielectric substrate results in a significant voltage buildup in the wafer, reducing the effective implant energy. Increasing the pulse voltage raises the dose/pulse, but at the cost of an expanded implant energy spread. Increasing the plasma ion density also raises the dose/pulse, but at the cost of a wider implant energy spread and a lower coupling efficiency. Increasing the substrate thickness reduces both the coupling efficiency and dose/pulse while broadening the energy spread. The large voltage generated across the dielectric substrate decreases the charge neutralization time significantly, reducing the possibility of gate oxide damage     

Spin and charge pumping in a quantum wire: the role of spin-flip scattering and Zeeman splitting

We investigate theoretically charge and spin pumps based on a linear configuration of quantum dots (quantum wire) which are disturbed by an external time-dependent perturbation. This perturbation forms an impulse which moves as a train pulse through the wire. It is found that the charge pumped through the system depends non-monotonically on the wire length, N. In the presence of the Zeeman splitting pure spin current flowing through the wire can be generated in the absence of charge current. Moreover, we observe electron pumping in a direction which does not coincide with the propagation direction of the pulse and the spin pumping direction (spin-charge separation). Additionally, on-site spin-flip processes significantly influence electron transport through the system and can also reverse the charge current direction.     

基于NPB的垂直构型有机发光晶体管的光电特性研究

通过将有机空穴阻挡材料BCP薄层插入垂直构型有机发光晶体管器件ITO/NPB（40nm）/Al（30nm）/NPB（20nm）/Alq₃（55nm）/Al中的不同位置对器件光电特性的影响来研究器件漏电流较大的原因以及器件中具体的载流子过程.充分证明了栅极注入的空穴对沟道中的电流有贡献.进而通过用LiF薄层修饰漏极来增强电子的注入并减小漏电流,得到了相对稳定的发光晶体管器件,其发光强度有很大提高并可很好地由栅极电压来进行调控.更换发光材料层容易得到不同颜色的发光晶体管. 关键词： 垂直构型有机发光晶体管（VOLET） 静电感应晶体管（SIT） N')" href="#">NPB （N N′-diphenyl-N')" href="#">N′-diphenyl-N N′-bis（1-naphtyl）-1')" href="#">N′-bis（1-naphtyl）-1 1′-biphenyl-4     

增强型AlGaN/GaN高电子迁移率晶体管高温退火研究

深入研究了两种增强型AlGaN/GaN高电子迁移率晶体管(HEMT)高温退火前后的直流特性变化.槽栅增强型AlGaN/GaN HEMT在500 ℃ N₂中退火5 min后,阈值电压由0.12 V正向移动到0.57 V,器件Schottky反向栅漏电流减小一个数量级.F注入增强型AlGaN/GaN HEMT在 400 ℃ N₂中退火2 min后,器件阈值电压由0.23 V负向移动到-0.69 V,栅泄漏电流明显增大.槽栅增强型器件退火过程中Schottky有效势垒     

Single-Parameter Quantum Pumping in Graphene Nanoribbons with Staggered Sublattice Potential

We present a theoretical study of quantum charge pumping in metallic armchair graphene nanoribbons using the Floquet-Green function method. A central part of the ribbon acting as the scattering region is supposed to have staggered sublattice potential to open a finite band gap. A single ac gate is asymmetrically applied to a part of the scattering region to drive the pumping. Corresponding to the gap edges, there are two pumped current peaks with opposite current directions, which can be reversed by changing the position of the ac gate relative to the scattering region. The effects of the parameters, such as the staggered sublattice potential, the driving frequency and the geometric parameters of the structure, on the pumping are discussed.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Shot noises of spin and charge currents in a ferromagnet-quantum-dot-ferromagnet system

We have investigated the shot noises of charge and spin current by considering the spin polarized electron tunneling through a ferromagnet-quantum-dot-ferromagnet system. We have derived the spin polarized current noise matrix, from which we can derive general expressions of shot noises associated with charge and spin currents. The spin and charge currents are intimately related to the polarization angles, and they behave quite differently from each other. The shot noise of charge current is symmetric about the gate voltage whose structure is modified by the Zeeman field considerably. There exists oscillations in spin current shot noise in the absence of source-drain bias at zero temperature, and it is asymmetric in the positive and negative regimes of sourcedrain voltage. The shot noise of spin current behaves quite differently from the shot noise of charge current, since the spin current components I _x ^s , I _y ^s oscillate sinusoidally with the frequency ω_γ in the γth lead, while the I _z ^s component of spin current is independent of time.