A generalized representation for dielectric dispersion

The generalized formulation for dielectric dispersion is extended for dielectrics exhibiting strongly overlapping arcs in the- complex plane. Subsequently, a novel network representation is developed whereby Negative Impedance Converters (NICs) are employed along with passive R-C elements. Satisfactory agreement is obtained in comparing the experimental results with those calculated using the new formulation.     

The distribution of trapping states at the Al/InP-oxide interface

The volume density of trapping states is derived throughout the metal-dielectric interface. This has been facilitated by equating the dielectric loss component to the tunneling conductance using a new relaxation time formulation. Subsequently, the trap distribution at the Al/InPO₄ interface has featured a peak of 1.15×10¹⁹ cm^–3 at about 15 Å from the Al contacting electrode. The new approach could be extended to deal with semiconductor-dielectric interfaces.     

Investigation of the low frequency dispersion of InP-oxide using a new Cole-Cole double-arc distribution

A new relaxation time distribution has been developed for double arc Cole-Cole plots in order to study the dispersion relation of InP-oxide. As suggested by a carrier injection model, the low frequency dispersion most likely originates from remaining In at the interface. The presence of In is a direct consequence of the Al electrode formation where the vapor-deposited electrode reacts with the InPO₄.     

Dielectric and interfacial properties of InP plasma-grown oxides

Methods of dielectric analysis have been employed to investigate the frequency dispersion of InP-oxide dielectric in MOS and MOM devices. The Cole-Cole empirical method has indicated a wide range of relaxation time for the interfacial polarization. This has been interpreted in terms of a model of carrier injection from the gate metal into the oxide gap states. The model is proposed in conjunction with the anomalous hysteresis in the MOM C-V characteristics and could be applied to other MIS systems.Formerly with the department of Engineering, Cambridge University, U.K.     

Photoinjection studies of ion-implantation-induced electron traps in MOS structures

Trapping centers related to P⁺ and B⁺ ions implanted in the SiO₂ layer as well as traps introduced into SiO₂ during boron implantation through the oxide into the silicon substrate have been investigated. The internal photoemission method has been used to estimate their capture cross section and total densityN _t .     

Mechanism of conductivity in metal-polymer-metal structures

Received: 25 September 1998 / Accepted: 25 November 1998 / Published online: 24 February 1999     

A thin-film transistor with a very thin a-Si:H layer and its application for an LC panel

One of the disadvantages of applying an a-Si:H thin-film transistor (TFT) to an active matrix-addressed liquid crystal (LC) panel is that a TFT with an a-Si:H has a very large photo-leakage current because of the high photo-conductivity of an a-Si:H itself.We have tried decreasing the photo-leakage current by varying the thickness of an a-Si:H layer (L) in TFTs and investigated the characteristics of TFTs, mainly drain voltage versus drain current containing photo-leakage current (I _ph).As a result, it is shown that lnI _ph is proportional to InL, and its gradient is 1.5–2.0. We assume that the thinner an a-Si:H layer is, the more effective the recombination of carriers at the interface states is forI _ph.We have applied TFT with a very thin a-Si:H layer (30nm) to a full-color active matrix-addressed LC panel for a moving picture display and realized a display of good quality under illuminated condition of 5×10⁴lx without a shading layer in it.     

Gadolinium oxide high-k gate dielectrics prepared by anodic oxidation

The growth and properties of gadolinium oxide (Gd₂O₃) films prepared by anodic oxidation were investigated. Uniform Gd₂O₃ thin film with good oxide quality was obtained. The X-ray diffraction (XRD) pattern of the Gd₂O₃ films showed that they had a poly-crystalline structure. The dielectric constants of Gd₂O₃ films oxidized at 30 and 60 V are 9.4 and 12.2, respectively. The equivalent oxide thickness (EOT) of the Gd₂O₃ stacked oxide is in the range of 5.8-9.4 nm. The MOS capacitor with Gd₂O₃ exhibits interesting electrical properties. Longer oxidation time reduced the leakage current density for 30 V anodic oxidation but increased the leakage current density for 60 V anodic oxidation. This work reveals that Gd₂O₃ could also be an alternative dielectric for Si substrate and therefore, might pave the way to fabricate CMOS devices in the future.     

Low field DC investigation of hot carrier trapping in silicon dioxide films

The experimental method used in this work is based upon the idea of nonavalanche injection of carriers heated by direct electric field. The structure consisted of an n-channel MOS transistor and two p-n junctions. The process of charge injection in this structure was investigated by studying the dependence of gate current on heating voltage. The trapping properties of the SiO₂ film were studied by monitoring the charging of the film during injection of electrons. The capture cross-sections, the trap centre concentrations and the dependence of the capture cross section on the electric field for fields between 1 MV/cm and 2.5 MV/cm were determined.     

Core-electron binding energies in atoms and monolayers adsorbed on metallic substrates

A Born-Haber cycle analysis of photoemission from atoms and monolayers adsorbed on metallic surfaces elucidates the effects of the substrate on the initial and final state contributions to measured core-electron binding energies. For rare gases both a dependence on the work function of the substrate and on the final state screening energy are identified. Depending on the relative magnitudes of the work function of the substrate and the ionization potential of the core-ionized atom, the screening charge may reside either in the substrate or on the adsorbate atom itself. Within the monolayer range, the coverage-dependence of the core-electron binding energy is shown to be largely a final-state effect. The Born-Haber cycle relating the Auger decay energy of an adsorbed core-ionized atom to that of a similar free atom is also presented. These formulations are tested using data for Xe adsorbed on Pd and Cs.     

The conductance and capacitance-frequency characteristics of Au/pyronine-B/p-type Si/Al contacts

The rectifying junction characteristics of the organic compound pyronine-B (PYR-B) film on a p-type Si substrate have been studied. The PYR-B has been evaporated onto the top of p-Si surface. The barrier height and ideality factor values of 0.67 ± 0.02 eV and 2.02 ± 0.03 for this structure have been obtained from the forward bias current-voltage (I-V) characteristics. The energy distribution of the interface states and their relaxation time have been determined from the forward bias capacitance-frequency and conductance-frequency characteristics in the energy range of ((0.42 ± 0.02) − E_v)-((0.66 ± 0.02) − E_v) eV. The interface state density values ranges from (4.21 ± 0.14) × 10¹³ to (3.82 ± 0.24) × 10¹³ cm⁻² eV⁻¹. Furthermore, the relaxation time ranges from (1.65 ± 0.23) × 10⁻⁵ to (8.12 ± 0.21) × 10⁻⁴ s and shows an exponential rise with bias from the top of the valance band towards the midgap.     

Tunneling magnetoresistance in Fe-oxide film

We fabricate Fe/Fe oxide granular film by DC sputtering and study the magnetic and transport properties in the insulator region. X-ray photoelectron spectroscopy and transmission electron microscopy confirm the coexistence of iron and Fe₂O₃. Accompanied with the nonlinear I-V curve and magnetic measurement, we investigate mechanism of sizable magnetoresistance in detail and found the spin in the interface has crucial contribution to the spin tunneling process.     

Investigating the effects of the interface defects on the gate leakage current in MOSFETs

The effects of the interface defects on the gate leakage current have been numerically modeled. The results demonstrate that the shallow and deep traps have different effects on the dependence relation of the stress-induced leakage current on the oxide electric field in the regime of direct tunneling, whereas both traps keep the same dependence relation in the regime of Fowler-Nordheim tunneling. The results also shows that the stress-induced leakage current will be the largest at a moderate oxide voltage for the electron interface traps but it increases with the decreasing oxide voltage for the hole interface traps. The results illustrate that the stress-induced leakage current strongly depends on the location of the electron interface traps but it weakly depends on the location of the hole interface traps. The increase in the gate leakage current caused by the electron interface traps can predict the increase, then decrease in the stress-induced leakage current, with decreasing oxide thickness, which is observed experimentally. And the electron interface trap level will have a large effect on the peak height and position.     

Annealing effect on tunneling magnetoresistance in MgO-based magnetic tunnel junctions with FeMn exchange-bias layer

MgO-based magnetic tunnel junctions were fabricated, with a thin pinned CoFeB layer in the unbalanced synthetic antiferromagnet part of the stack FeMn/CoFe/Ru/CoFeB. Inverted and normal tunneling magnetoresistance (TMR) values occur at low and high annealing temperatures (T_a), respectively. The TMR ratio remains inverted up to T_a=300 °C and it becomes normal around T_a=350 °C. The exchange bias of FeMn disappears at high T_a. The sign reversal of the TMR ratio is mainly attributed to the disappearance of the exchange bias due to manganese diffusion during the annealing process.     

A Novel Super-Junction Lateral Double-Diffused Metal--Oxide--Semiconductor Field Effect Transistor with n-Type Step Doping Buffer Layer

A novel super-junction lateral double-diffused metal-oxide--semiconductor field effect transistor （SJ-LDMOSFET） with n-type step doping buffer layer is proposed. The step doping buffer layer almost completely eliminates the substrate-assisted depletion effect, modulates lateral electric field and achieves nearly uniform surface field. On the other hand, the buffer layer also provides another conductive path and reduces on-state resistance. In short, the proposed LDMOSFET improves trade-off performance between breakdown voltage （B V） and specific on-state resistance Ron,sp. Compared with the conventional SJ-LDMOSFET, the simulation results indicate that the BV of the SSJ-LDMOSFET is increased from saturation voltage 121.7V to 644.9 V; at the same time, the specific on-state resistance is decreased from 0.314 Ω.cm^2 to 0.14 Ω.cm^2 by virtue of 3D numerical simulations using ISE when the drift region length and the step number are taken as 48μm and 3, respectively.     

Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO₂/HfSiO/SiO₂ trilayer and HfTiSiO/SiO₂ bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO₂ underlayers degrades the EOT-J_g characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO₂ capping for improving EOT-J_g characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10⁻² A/cm² for a TiO₂/HfSiO/SiO₂ trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.     

Quantum fluctuations in a single electron box

Recent experiments have demonstrated that the numbern of additional electrons on a small metallic island is a staircase function of a continuous external chargen _x for temperaturesT small compared to the single electron charging energyU. We show that the finite conductanceg of the tunnel barrier connecting the island to the external gate gives rise to quantum fluctuations inn which lead to a smearing of the staircase even at zero temperature. In the experimentally relevant case of wide junctions and in the limit of small conductanceg1 the slope <n>/n _x at the turning point between two plateaus saturates at a finite value of order 1/g asT0 instead of diverging likeU/T as predicted with thermal fluctuations only. The experimentally observed broadening however is still much larger which is probably due to extrinsic effects.     

The effect of interface states, excess capacitance and series resistance in the Al/SiO2/p-Si Schottky diodes

The current-voltage (I-V) characteristics of Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO₂ interface. The density of interface states (N_ss) distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) at room temperature for the Schottky diode on the order of ≅4 × 10¹³ eV⁻¹ cm⁻²_. These high values of N_ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The N_ss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V, C-V and G-V characteristics of SD are affected not only in N_ss but also in series resistance (R_s), and the location of N_ss and R_s has a significant on electrical characteristics of Schottky diodes.     

Inversion layer resistance in silicon inversion layer solar cells

The inversion layer resistance is very important for metal-insulator-semiconductor inversion layer (MIS/IL) solar cells, and usually it is the main part of the series resistance. It is found that the inversion layer resistance and the junction depth are determined by the operating voltage for an MIS/IL solar cell. On the basis of MIS theory, a general relationship between the operating voltage and the inversion layer resistance (and the junction depth) has been investigated. Practical computations have been done for MIS/IL solar cells with a silicon nitride insulator layer. It is found that the inversion layer resistance has a minimum value for operating voltage near 0.4 V, and the junction depth decreases monotonically with the increase of the operating voltage.