BIST-based test and diagnosis of FPGA logic blocks

We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable     

Online BIST and BIST-based diagnosis of FPGA logic blocks

We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.     

Cumulative balance testing of logic circuits

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation, provably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Vector sets for exhaustive testing of logic circuits

(L, d)-universal sets are useful for exhaustively testing logic circuits with a large number of functional components, designed so that every functional component depends on at most d inputs. Randomized and deterministic constructions of ( L, d)-universal test sets are presented, and lower and upper bounds on the optimal sizes of such sets are proven. It is also proven that the design of an optimal exhaustive test set for an arbitrary logic circuit is an NP-complete problem     

Circuit internal logic analysis with electric force microscope- (EFM-) testing

In this paper the well known electron beam testing techniques stroboscopic voltage contrast and logic state mapping are realized for an EFM-testing system. These testing techniques allow an advanced logic analysis of digital circuits. They are based on a linear interaction, a pulse sampled measurement method and a scanned EFM-tip. First measurement results are shown on an integrated bus structure of 2 μm feature size with applied clock signals at few megahertz frequencies pointing out the ability for simultaneous temporal and spatial frequency measurements with EFM-testing, as well. Further improvements promise the applicability of these proven testing techniques in integrated circuits with structure dimensions beyond the limits of electron beam testers.     

Fast test generation and partial testing for combinational logic circuits

A simple, yet effective fast test generation algorithm by using the real value boolean difference is given for combinational logic circuits along with a short review of several fast test generation algorithms. Because no recursive operation is involved, it can be carried out as a parallel algorithm. In the second part of this paper, the concept of the partial testing is discussed. A new partial testing method, weighted point testing, is presented in this paper. Every line or node in the combinational logic circuit has a weight assigned to it. The weight at a point is determined by several factors, such as the fault occurrence found by experience or prior-knowledges, the number of fan-in or fan-out at that point, and the depth of the point in the circuit. Only those points with relatively high weights are considered in the test generation and testing. Because testing is more effectively done and directed to the point, the test coverage is higher.     

VLSI logic design with logic programming and knowledge-basetechnology

An approach to VLSI logic design using partial and general structural specifications in addition to behavioral specifications is developed. This approach requires a new style of programming technique, especially if a universal solution procedure for all types of architectures is needed. Knowledge of the design process involves unification of the heterogeneous (i.e. behavior and structure) information between a system and its parts, as well as representation of functional modules in order to ensure their reusability in an efficient manner. Following these strategies, a logic synthesis expert system, ProLogic, is developed, and the system is evaluated using MPU-type VLSIs. It is found that the universal connecting procedure for any compound functional module that unifies the behavioral and structural specifications between a total module and its parts improves logic design efficiency by a factor of 2 and that logic programming, object-oriented frames, and rule bases implemented in ProLogic improve software productivity by a factor of 5     

On robust two-pattern testing of one-dimensional CMOS iterative logic arrays

In this paper a graph model and a method to construct robust (for the first time in open literature) as well as non-robust two-pattern tests for one-dimensional iterative logic arrays (ILAs) are presented. Exploring the graph structure we can find two-pattern tests that can be applied with a constant or linear number of test vectors to all the ILA cells. Such tests are subsequently characterized as robust or non-robust two-pattern tests.     

A rapid optoelectronic half-adder logic composed of a pair of GaAsmetal-semiconductor-metal photodetectors

A novel optoelectronic half-adder logic, composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PDs), is reported. The optoelectronic logic utilizes the features of the MSM-PD for both polarities of electrical bias (positive and negative). Without any other active devices such as transistors, the output delay time is short, less than 100 ps for the entire half-adder operation, which assures a very fast arithmetic operation     

Avalanche breakdown in silicon devices for contactless logic testing and optical interconnect

A silicon p–n junction that is biased in avalanche breakdown mode emits visible light. Although the efficiency of such silicon emitters is poor, their ability to modulate at GHz frequencies make them a good choice for many applications including optical interconnect and optical contactless logic testing. Results demonstrate the feasibility of an all silicon optical interconnect system and an all silicon contactless testing methodology using the silicon light emitter and standard silicon detectors. The development of truly efficient silicon light emitting would enable many new applications.     

双有限域模乘和模逆算法及其硬件实现

有限域上的模乘和模逆运算是椭圆曲线密码体系的两个核心运算。该文在Blakley算法的基础上提出一种radix-4快速双有限域模乘算法,该算法采用Booth编码技术将原算法的迭代次数减少一半,并利用符号估计技术简化约减操作;在扩展Euclidean求逆算法的基础上提出一种能够同时支持双有限域运算的高效模逆算法,该算法不仅避免了大整数比较操作,而且提高了算法在每次迭代过程中的移位效率。然后针对这两种算法特点设计出一种能够同时完成双有限域上模乘和模逆操作的统一硬件结构。实现结果表明：256位的模乘和模逆统一硬件电路与同类型设计相比较,在电路面积没有增加的情况下,模乘运算速度提高68%,模逆运算的速度也提高了17.4%。     

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.     

Fault characterization, testing considerations, and design fortestability of BiCMOS logic circuits

The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented     

Configuring a boundary scan chain for optimal testing of non-scan logic clusters

Testing of boards containing a mixture of boundary scan components and clusters of non-boundary scan logic is an interesting problem. If a tester cannot contact the non-scan logic clusters, the inputs and outputs of on board boundary scan devices may be used as virtual access points to test the clusters. In that case, the time required for testing the clusters depends on how the boundary scan chips are connected into a longer scan chain. This paper presents a technique for configuring a chain of boundary scan chips to minimize the test time for nonscan logic clusters.     

Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies

In advanced technologies an increasing proportion of defects manifest themselves as small delay faults. Most of today’s advanced delay-fault algorithms are able to propagate those delay faults which create logic or glitch faults. An algorithm is proposed for circuit fault diagnosis in deep sub-micron technology to propagate the actual timing faults as well as those delay faults that eventually create logic faults to the primary outputs. Unlike the backtrack algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach propagates the fault from the fault site by mapping a nine-valued voltage model on top of a five-valued voltage model. In such a forward approach, accuracy is greatly increased since all composite syndromes at all faulty outputs are considered simultaneously. As a result, the proposed approach is applicable even when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is considerable.     

Method for rapid testing of thermo-mechanical characteristics of solder joints

The creep behavior of alternative soft solder alloys is not, as a rule, well known. This characteristic is however very important for the prediction of a joint's long-term reliability. Conventional test methods are often impractical, slow and deliver only qualitative results. The new testing method presented is able to provide very fast quantitative values of thermo-mechanical characteristics. This paper shows latest results, comparison with standard testing, investigation of high temperature applications and new fields of use.