热空穴应力下LDD nMOSFET中GIDL电流退化特性研究*

本文通过GIDL电流参数IDIFF对空穴应力下LDD nMOSFET中的GIDL电流退化进行了深入研究。IDIFF是在相同VDG下漏电压VD=1.4V和栅电压VG=-1.4V两种情形下的GIDL电流之差。空穴陷落在栅漏交叠区的氧化层中导致GIDL电流退化。这些陷落的空穴减小了上述两种对称的测试情形下的横向电场差ΔEX从而使得IDIFF表小。从GIDL电流中提取的IDIFF随着应力时间t的增加而减小。IDIFF的退化量ΔIDIFF,MAX与应力时间成幂指数关系：ΔIDIFF,MAX∝tm, m=0.3. 并用热电子应力实验验证了HHS实验中的相关物理机理。     

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

GIDL应力下超薄栅氧LDD NMOS器件退化

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现，短沟薄栅氧LDD nMOSFET（Lg=0.18μm，Tox=3.2nm）在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子（DAHC）应力下的器件寿命要短，这与通常认为的DAHC应力（最大衬底电流应力）下器件退化最严重的理论不一致．因此，这种热载流子应力导致的器件退化机理不能用幸运电子模型（LEM）的框架理论来解释．认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子，在Si-SiO2界面产生界面陷阱(界面态)的区域，由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的．     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法,建立了适用于亚微米、深亚微米的LDD MOSFET输出I-V特性解析模型,模型中重点考虑了衬底电流的作用.模拟结果与实验有很好的一致性.该解析模型计算简便,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述,因此适用于器件的优化设计及可靠性分析.     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法 ,建立了适用于亚微米、深亚微米的 L DD MOSFET输出 I- V特性解析模型 ,模型中重点考虑了衬底电流的作用 .模拟结果与实验有很好的一致性 .该解析模型计算简便 ,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述 ,因此适用于器件的优化设计及可靠性分析     

一种用于提取LDD结构n-MOSFET热载流子应力下界面陷阱产生的改进方法

提出了一种新的基于电荷泵技术和直流电流法的改进方法,用于提取LDDn MOSFET沟道区与漏区的界面陷阱产生.这种方法对于初始样品以及热载流子应力退化后的样品都适用.采用这种方法可以准确地确定界面陷阱在沟道区与漏区的产生,从而有利于更深入地研究LDD结构器件的退化机制.     

应力下LDD nMOSFET栅控产生电流退化特性研究

研究了LDD nMOSFET栅控产生电流在电子和空穴交替应力下的退化特性。电子应力后栅控产生电流减小,相继的空穴注人中和之前的陷落电子而使得产生电流曲线基本恢复到初始状态。进一步发现产生电流峰值在空穴应力对电子应力引发的退化的恢复程度与阈值电压和最大饱和漏电流不同。电子应力中陷落电子位于栅漏交叠区附近的沟道侧I区和LDD侧的II区中氧化层中。GIDL应力中,空穴注入进II区中和了陷落电子,使得产生电流的退化基本得到恢复,但这些空穴并未有效中和I区中的陷落电子,因此阈值电压和最大饱和漏电流退化恢复的程度较小,分别为20%和7%。     

Degradation of oxides and oxynitrides under hot hole stress

The impact of nitridation on hot hole injection and the induced degradation is quantitatively studied by comparing the behavior of a control oxide and oxynitrides. The oxynitride is prepared by either annealing the oxide in N₂O or growing directly in N₂ O. The pMOSFET's are uniformly stressed by using the substrate hot hole injection technique. The physical quantities analyzed include the hole injection current, the density of created interface states and the density of trapped holes. It is found that a 30 min annealing in N₂ O at 950°C can enhance the effective barrier for hole injection by 0.6 eV. However, the interface state generation during the injection is insensitive to nitridation. The continuing degradation post the hole injection is also investigated. This includes a poststress interface state build-up and the generation of new precursors for interface states. The nitridation reduces the poststress degradation considerably. Where it is necessary, the hole induced degradation is compared with that induced by electrons. The applicability of the models proposed for oxynitrides to the present results is examined     

LDD NMOS器件热载流子退化研究

对LDD(轻掺杂漏)NMOS器件的热载流子退化特性进行了研究,发现LDD NMOS器件的退化呈现出新的特点.通过实验与模拟分析,得出了热载流子应力下LDD NMOS退化特性不同于常规(非LDD)NMOS的物理机制.并通过模拟对此观点进行了验证.     

A new approach for modeling of current degradation in hot-electrondamaged LDD NMOSFETs

An analytical model describing current degradation in hot-electron damaged LDD NMOSFETS is proposed. The basic idea of the model is that the drain current degradation can be explained in terms of an increase in the parasitic resistance only. Good agreement with measured data over at least three decades of stress time is obtained with our model     

一种用于提取LDD结构n-MOSFET热载流子应力下界面陷阱产生的改进方法

提出了一种新的基于电荷泵技术和直流电流法的改进方法,用于提取LDD n-MOSFET沟道区与漏区的界面陷阱产生.这种方法对于初始样品以及热载流子应力退化后的样品都适用.采用这种方法可以准确地确定界面陷阱在沟道区与漏区的产生,从而有利于更深入地研究LDD结构器件的退化机制.     

The base current degradation of poly-emitter BJTs under AC stress

A simple model for the analysis of the ac stress effect in poly-emitter bipolar transistors is presented. Apart from the reverse-bias induced hot-carrier effects, the forward-bias recovery effect is a key factor under ac stress, it obviously suppresses the base current degradation of the device which is caused during the reverse-bias periods. In this work, we derived the relationship between the excess base current and the stress time for different ac stress conditions. This model is verified with experimental results.<>     

用于LDD和SST的SiO2边墙干法腐蚀工艺研究

本文从干法腐蚀角度出发,首先从数学上分析了多晶硅角度,SiO_2边墙的宽度和高度,衬底损失与各工艺参数间的关系,指出边墙的宽度和高度分别取决于多晶硅的角度和过腐蚀量。在Tegal1512e设备上,采用Cl_2、SF_6、N_2混合气体,开发了多晶硅干法腐蚀工艺,讨论了LDD的正胶掩膜及SST的SiO_2掩膜对工艺的不同影响。SEM分析发现了SF_6气体腐蚀的各向同性。在Tegal903e设备上,采用CHF_3、SF_6、He混合气体,开发了SiO_2边墙干法腐蚀工艺,研究了腐蚀的各向异性,辐射损伤,选择比,均匀性及重复性的控制方法。取得的工艺结果为,腐蚀速率(?)_(sio_2)≈400nm/min,均匀性U≤±5％,选择比S_(f8)>10,工序能力指数C_p>1。     

GaAs MESFET的热电子应力退化

进行GaAs MESFET的热电子应力试验,在24V≤VDS≤28V,-5．5≤VGS≤-4V的应力条件下,热电子效应将导致GaAs MESFET直流参数的严重退化。退化模式主要表现为饱和漏电流如s减小,跨导gn减小,夹断电压Vp增大,击穿电压增大。从微波性能方面来看,热电子效应器件的输出功率增益大幅度下降。退化机理主要是栅漏区表面及栅边缘俘获负电荷。     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的L DD MOSFET.在以双曲正切函数描述的I- V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.