InAs/GaAs和InAs/InxGa1-xAs/GaAs纳米线异质结构的生长研究

利用金辅助金属有机化学气相沉淀法(MOCVD)在GaAs(111)B衬底上分别制备了InAs/GaAs和InAs/In _{x Ga1-xAs/GaAs(0≤x≤1)纳米线异质结构.实验结果显示,直接生长在GaAs纳米线上的InAs纳米线生长方向杂乱或者沿着GaAs纳米线侧壁向衬底方向生长,生长的含有In x Ga1-xAs组分渐变缓冲段的InAs/In x Ga1-x关键词： 纳米线异质结构 xGa1-xAs')" href="#">InxGa1-xAs 组分渐变缓冲层 金属有机化学气相沉淀法}     

Template preparation of Pt nanowire array electrode on Ti/Si substrate for methanol electro-oxidation

Platinum (Pt) nanowire array electrode is obtained by dc electrodeposition of Pt into the pores of anodic aluminum oxide (AAO) template on Ti/Si substrate. Transmission electron microscope (TEM) examination shows all the nanowires have uniform diameter of about 30 nm. The brush shapes Pt nanowire array electrode can be seen clearly by field emission scanning electron microscope (FESEM). Pt nanowire array electrode gives the X-ray diffraction (XRD) pattern of face-centered cubic (fcc) crystal structure. The electro-oxidation of methanol on this electrode is investigated at room temperature by cyclic voltammetry. The results demonstrated that the Pt nanowire array electrode will have good potential applications in portable power sources.     

Growth and characterization of GaAs/InxGa1-xAs/GaAs axial nanowire heterostructures with symmetrical heterointerfaces

We report on the Au-assisted vapour-liquid-solid （VLS） growth of GaAs/InxGal xAs/GaAs （0.2 ≤ x ≤1） axial double-heterostructure nanowires on GaAs （ 111 ） B substrates via the metal-organic chemical vapor deposition （MOCVD） technique. The influence of the indium （In） content in an Au particle on the morphology of nanowires is investigated systematically. A short period of pre-introduced In precursor before the growth of InxGal xAs segment, coupled with a group III precursor interruption, is conducive to obtaining symmetrical heterointerfaces as well as the desired In/Ga ratio in the InxGa1-xAs section. The nanowire morphology, such as kinking and tapering, are thought to be related to the In composition in the catalyst alloy as well as the VLS growth mechanism.     

硅衬底GaN基LED N极性n型欧姆接触研究

在Si衬底GaN基垂直结构LED的N极性n型面上,利用电子束蒸发的方法制作了Ti/Al电极,通过了I-V曲线研究了有无AlN缓冲层对这种芯片欧姆接触的影响.结果显示,去除AlN缓冲层后的N极性n型面与Ti/Al电极在500到600 ℃范围内退火才能形成欧姆接触.而保留AlN缓冲层的N极性n型面与Ti/Al电极未退火时就表现为较好的欧姆接触,比接触电阻率为2×10^-5 Ω·cm²,即使退火温度升高至600 ℃,也始终保持着欧姆接触特性.因此,AlN缓冲层的存在是Si衬底GaN基垂直结构LED获得高热稳定性n型欧姆接触的关键. 关键词： 硅衬底 N极性 AlN缓冲层 欧姆接触     

Horizontal InAs nanowire transistors grown on patterned silicon-on-insulator substrate

High-density horizontal InAs nanowire transistors are fabricated on the interdigital silicon-on-insulator substrate. Hexagonal InAs nanowires are uniformly grown between face-to-face (111) vertical sidewalls of neighboring Si fingers by metal-organic chemical vapor deposition. The density of InAs nanowires is high up to 32 per group of silicon fingers, namely an average of 4 nanowires per micrometer. The electrical characteristics with a higher on/off current ratio of 2×10⁵ are obtained at room temperature. The silicon-based horizontal InAs nanowire transistors are very promising for future high-performance circuits.     

SiO2/Si衬底上石墨烯的制备与结构表征

在分子束外延(MBE)设备中,利用直接沉积C原子的方法在覆盖有SiO₂的Si衬底(SiO₂/Si)上生长石墨烯,并通过Raman光谱和近边X射线吸收精细结构谱等实验技术对不同衬底温度(500℃,600℃,700℃,900℃,1100℃,1200℃)生长的薄膜进行结构表征.实验结果表明,在衬底温度较低时生长的薄膜是无定形碳,在衬底温度高于700℃时薄膜具有石墨烯的特征,而且石墨烯的结晶质量随着衬底温度的升高而改善,但过高的衬底温度会使石墨烯质量降低.衬底温度为1100℃时结晶质量最好.衬底温度较低时C原子活性较低,难以形成有序的C-sp²六方环.而衬底温度过高时(1200℃),衬底表面部分SiO₂分解,C原子与表面的Si原子或者O原子结合而阻止石墨烯的形成,并产生表面缺陷导致石墨烯结晶变差.     

内嵌镧原子的磁性硅纳米线的第一性原理研究

基于密度泛函理论,系统研究了由两个La@Si_(16)组装而成的高度稳定的管状二聚体La_2@Si_(32)团簇.电子结构分析显示,内嵌La原子诱导的类sp~2杂化对于提高管状Si_(32)的稳定性至关重要.Mülliken布局分析显示,La_2@Si_(32)的总磁矩为2 μ_B,主要来源于两个La原子和第三、第六层的八个Si原子;电荷是由Si原子转移到了La原子上.此外,通过连接一系列La_2@Si_(32)单体而获得了一类组装的硅纳米线La@SiNW,研究结果显示La@SiNW具有金属导电特性,其总磁矩为2 μ_B.上述特征暗示具有磁性的La_2@Si_(32)和La@SiNW可能在自旋电子器件和高密度磁记录材料方面具有潜在的应用前景.     

Electronic properties of InAs/GaAs nanowire superlattices

The electronic properties of strained InAs/GaAs nanowire superlattices are computed using a semi-empirical sp³d⁵s^* tight-binding model, taking strains, piezoelectric fields and image charge effects into account. Strain relaxation appears to be efficient in nanowire heterostructures, but is highly inhomogeneous in thin InAs layers. It digs a well in the conduction band that traps the electrons at the surface of the nanowires. This likely decreases the oscillator strength and might ease the capture of the electrons by nearby surface defects.     

Growth of InAs/GaAs quantum dots on germanium-on-insulator-on-silicon substrate for silicon photonics

We report the growth of self-assembled InAs/GaAs quantum dots (QDs) on germanium-on-insulator-on-silicon (GeOI/Si) substrate by antimony-mediated metal organic chemical vapor deposition. The influence of various growth procedures for the GaAs buffer layer on the QD formation and optical quality was investigated. We obtained QDs with density above 10¹⁰ cm⁻², and ground state emission in the 1.3 μm band at room temperature. These results demonstrate the promising suitability of germanium-on-insulator for the monolithic integration of QD-based and other GaAs-based photonic devices on silicon.     

双势垒InAs/InP纳米线异质结热电子制冷机

研究了具有不同温度和不同化学势的两个热库中电子通过一个双势垒InAs/InP纳米线异质结进行的传输.利用传输矩阵法得到了电子的传输概率,进而计算得到电子传输所产生的热流.通过数值计算给出了热电子制冷机的性能特征曲线.进一步分析了势垒宽度和势阱宽度对制冷机工作性能的影响.研究发现,当势阱宽度一定时,随着势垒宽度变大共振中心能级的位置变大,共振能级宽度变小,同一偏压对应的制冷率变小,相对制冷系数变大.当势垒宽度一定时,随着势阱宽度变大,同一偏压对应的相对制冷系数变小.当势垒和势阱宽度同时变化时,得到的曲线与势垒宽度一定势阱宽度变化时得到的曲线基本相似.这表明制冷率和相对制冷系数主要受势阱宽度变化的影响.     

Growth of high-crystallinity uniform GaAs nanowire arrays by molecular beam epitaxy

The self-catalyzed growth of Ga As nanowires(NWs) on silicon(Si) is an effective way to achieve integration between group III–V elements and Si. High-crystallinity uniform Ga As NW arrays were grown by solid-source molecular beam epitaxy(MBE). In this paper, we describe systematic experiments which indicate that the substrate treatment is crucial to the highly crystalline and uniform growth of one-dimensional nanomaterials. The influence of natural oxidation time on the crystallinity and uniformity of Ga As NW arrays was investigated and is discussed in detail. The Ga As NW crystallinity and uniformity are maximized after 20 days of natural oxidation time. This work provides a new solution for producing high-crystallinity uniform III–V nanowire arrays on wafer-scale Si substrates. The highly crystalline uniform NW arrays are expected to be useful for NW-based optical interconnects and Si platform optoelectronic devices.     

金辅助催化方法制备GaAs和GaAs/InGaAs纳米线结构的形貌表征及生长机理研究

利用金（Au）辅助催化的方法,通过金属有机化学气相沉积技术制备了GaAs纳米线及GaAs/InGaAs纳米线异质结构.通过对扫描电子显微镜（SEM）测试结果分析,发现温度会改变纳米线的生长机理,进而影响形貌特征.在GaAs纳米线的基础上制备了高质量的纳米线轴、径向异质结构,并对生长机理进行分析.SEM测试显示,GaAs/InGaAs异质结构呈现明显的“柱状”形貌与衬底垂直,InGaAs与GaAs段之间的界面清晰可见.通过X射线能谱对异质结样品进行了线分析,结果表明在GaAs/InGaAs轴向纳米线异质结构样品中,未发现明显的径向生长.从生长机理出发分析了在GaAs/InGaAs径向纳米线结构制备过程中伴随有少许轴向生长的现象.     

Growth and characterization of DyP/GaAs and DyAs/GaAs-based heterostructures and superlattices

Details of the structural and electrical properties of epitaxial DyP/GaAs and DyAs/GaAs is reported. DyP is lattice matched to GaAs, with a room temperature mismatch of less than 0.01%. DyAs, on the other hand, has a mismatch of nearly 2.4%. Both DyP and DyAs have been grown by solid source MBE using custom designed group V thermal cracker cells and group III high-temperature effusion cells. High-quality DyP and DyAs epilayers, as determined by XRD, TEM, and AFM analysis, were obtained for growth temperatures ranging from 500°C to 600°C with growth rates between 0.5 and 0.7 μm/h. The DyP epilayers are n-type with measured electron concentrations of the order of 3×10²⁰ to 4×10²⁰ cm⁻³, with room temperature mobilities of 250–300 cm²/V s, and with a barrier height of 0.75 eV to GaAs. The DyAs epilayers are also n-type with concentration of 1×10²¹ to 2×10²¹ cm⁻³, with mobilities between 25 and 40 cm²/V s. DyP is stable in air with no apparent oxidation taking place, even after months of ambient exposure to untreated air.     

基于MOCVD三步生长的GaAs/Si外延技术EI北大核心CSCD

在硅(Si)上外延生长高质量的砷化镓(GaAs)薄膜是实现硅基光源单片集成的关键因素。但是,Si材料与GaAs材料之间较大的晶格失配、热失配等问题对获得高质量的GaAs薄膜造成了严重影响。本文利用金属有机化学气相沉积(MOCVD)技术开展Si基GaAs生长研究。通过采用三步生长法,运用低温成核层、高温GaAs层与循环热退火等结合的方式,进一步降低Si基GaAs材料的表面粗糙度和穿透位错密度。并利用X射线衍射(XRD)ω-2θ扫描追踪采用不同方法生长的样品中残余应力的变化。最终,在GaAs低温成核层生长时间62 min(生长厚度约25 nm)时,采用三步生长、循环热退火等结合的方式获得GaAs(004)XRD摇摆曲线峰值半高宽(FWHM)为401″、缺陷密度为6.8×10^(7) cm^(-2)、5μm×5μm区域表面粗糙度为6.71 nm的GaAs外延材料,在材料中表现出张应力。     

The effect of substrate on magnetic properties of Co/Cu multilayer nanowire arrays

Ordered Co/Cu multilayer nanowire arrays have been fabricated into anodic aluminium oxide templates with Ag and Cu substrate by direct current electrodeposition. This paper studies the morphology, structure and magnetic properties by transmission electron microscopy, selective area electron diffraction, x-ray diffraction, and vibrating sample magnetometer. X-ray diffraction patterns reveal that both as-deposited nanowire arrays films exhibit face-centred cubic structure. Magnetic measurements indicate that the easy magnetization direction of Co/Cu multilayer nanowire arrays films on Ag substrate is perpendicular to the long axis of nanowire, whereas the easy magnetization direction of the sample with Cu substrate is parallel to the long axis of nanowire. The change of easy magnetization direction attributed to different substrates, and the magnetic properties of the nanowire arrays are discussed.     

纳米尺度下Si/Ge界面应力释放机制的分子动力学研究

采用分子动力学方法研究了纳米尺度下硅(Si)基锗(Ge)结构的Si/Ge界面应力分布特征,以及点缺陷层在应力释放过程中的作用机制.结果表明:在纳米尺度下, Si/Ge界面应力分布曲线与Ge尺寸密切相关,界面应力下降速度与Ge尺寸存在近似的线性递减关系;同时,在Si/Ge界面处增加一个富含空位缺陷的缓冲层,可显著改变Si/Ge界面应力分布,在此基础上对比分析了点缺陷在纯Ge结构内部引起应力变化与缺陷密度的关系,缺陷层的引入和缺陷密度的增加可加速界面应力的释放.参考对Si/Ge界面结构的研究结果,可在Si基纯Ge薄膜生长过程中引入缺陷层,并对其结构进行设计,降低界面应力水平,进而降低界面处产生位错缺陷的概率,提高Si基Ge薄膜质量,这一思想在研究报道的Si基Ge膜低温缓冲层生长方法中初步得到了证实.     

Wetting layers effect on InAs/GaAs quantum dots

FEM combining with the K·P theory is adopted to systematically investigate the effect of wetting layers on the strain-stress profiles and electronic structures of self-organized InAs quantum dot. Four different kinds of quantum dots are introduced at the same height and aspect ratio. We found that 0.5 nm wetting layer is an appropriate thickness for InAs/GaAs quantum dots. Strain shift down about 3%∼4.5% for the cases with WL (0.5 nm) and without WL in four shapes of quantum dots. For band edge energy, wetting layers expand the potential energy gap width. When WL thickness is more than 0.8 nm, the band edge energy profiles cannot vary regularly. The electron energy is affected while for heavy hole this impact on the energy is limited. Wetting layers for the influence of the electronic structure is obviously than the heavy hole. Consequently, the electron probability density function spread from buffer to wetting layer while the center of hole's function moves from QDs internal to wetting layer when introduce WLs. When WLs thickness is larger than 0.8 nm, the electronic structures of quantum dots have changed obviously. This will affect the instrument's performance which relies on the quantum dots' optical properties.     

Influence of AlN buffer layer thickness on structural properties of GaN epilayer grown on Si (111) substrate with AlGaN interlayer

We present the growth of GaN epilayer on Si (111) substrate with a single AlGaN interlayer sandwiched between the GaN epilayer and AlN buffer layer by using the metalorganic chemical vapour deposition. The influence of the AlN buffer layer thickness on structural properties of the GaN epilayer has been investigated by scanning electron microscopy, atomic force microscopy, optical microscopy and high-resolution x-ray diffraction. It is found that an AlN buffer layer with the appropriate thickness plays an important role in increasing compressive strain and improving crystal quality during the growth of AlGaN interlayer, which can introduce a more compressive strain into the subsequent grown GaN layer, and reduce the crack density and threading dislocation density in GaN film.     

Experimental extraction of stern-layer capacitance in biosensor detection using silicon nanowire field-effect transistors

Accurate diagnose of a disease in the early stage is critical to treat the disease properly. To this end, a multitude of biosensors with advanced technologies have been developed to detect the number of biomolecules precisely. In this work, we propose a method for extracting the Stern layer capacitance (C_stern) using the experimental data of silicon nanowire ion-sensitive field-effect transistors (ISFETs) to help improve the accurate detection of target molecules. The proposed method was applied to both pH and virus sensing scheme, and the C_stern value of pH and a virus were extracted as 32 and 26 μF/cm², respectively. These findings indicated that the extracted C_stern was affected by the size of the ion and protein, which also was verified by a computer-aided simulation. These insights would be useful in the development of charge-based ISFET biosensors.