Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Silicon nanoparticle charge trapping memory cell

A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO) active layer is deposited by atomic layer deposition (ALD), preceded by Al₂O₃ which acts as the gate, blocking and tunneling oxide. Spin coating technique is used to deposit Si NPs across the sample between Al₂O₃ steps. The Si nanoparticle memory exhibits a threshold voltage (V_t) shift of 2.9 V at a negative programming voltage of –10 V indicating that holes are emitted from channel to charge trapping layer. The negligible measured V_t shift without the nanoparticles and the good re‐ tention of charges (>10 years) with Si NPs confirm that the Si NPs act as deep energy states within the bandgap of the Al₂O₃ layer. In order to determine the mechanism for hole emission, we study the effect of the electric field across the tunnel oxide on the magnitude and trend of the V_t shift. The V_t shift is only achieved at electric fields above 1 MV/cm. This high field indicates that tunneling is the main mechanism. More specifically, phonon‐assisted tunneling (PAT) dominates at electric fields between 1.2 MV/cm < E < 2.1 MV/cm, while Fowler–Nordheim tunneling leads at higher fields (E > 2.1 MV/cm). (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Permeation barrier properties of an Al2O3/ZrO2 multilayer deposited by remote plasma atomic layer deposition

We report the permeation barrier properties of Al₂O₃/ZrO₂ multi-layers deposited by remote plasma atomic layer deposition. Electrical Ca degradation tests were performed to derive the water vapor transmission rate (WVTR) of Al₂O₃, ZrO₂ and Al₂O₃/ZrO₂ multi-layers at 50 °C and 50% relative humidity (RH). Al₂O₃/ZrO₂ multi-layers exhibit better barrier properties than Al₂O₃ and ZrO₂ layers, and when more individual layers were deposited in the same total thickness, the WVTR value was reduced further, indicating a better barrier property. The WVTR of the Al₂O₃ and ZrO₂ layers were 9.5 × 10⁻³ and 1.6 × 10⁻² g/m² day, respectively, but when deposited alternatively with 1 cycle of each layer, the WVTR decreased to 9.9 × 10⁻⁴ g/m² day. X-ray diffraction results indicated that ZrO₂ has a monoclinic structure but Al₂O₃ and Al₂O₃/ZrO₂ multi-layers show an amorphous structure. Cross sectional Al₂O₃/ZrO₂ multi-layer structures and the formation of a ZrAl_xO_y phase are observed by transmission electron microscopy (TEM). X-ray photoelectron spectrometry (XPS) results indicate that Al₂O₃ and ZrO₂ contain 33.7% and 37.8%, respectively, Al–OH and Zr–OH bonding. However, the ZrAl_xO_y phase contained 30.5% Al–OH and Zr–OH bonding. The results of transmittance measurement indicate that overall, Al₂O₃, ZrO₂ and Al₂O₃/ZrO₂ multi-layers show high transmittance greater than 80% in the visible region.     

The charge storage of the nc—Si layer

Sandwiched structures (a-SiN_x/a-Si/a-SiN_x) have been fabricated by the plasma enhanced chemical vapour deposition technique. A Si nanocrystal (nc-Si) layer was formed by crystallization of an a-Si layer according to the constrained crystallization principle after quasi-static thermal annealing at 1100℃ for 30 min. Transmission electron microscopy (TEM) and Raman scattering spectroscopy clearly demonstrated that nc-Si grains were formed in the as-deposited a-Si layer after annealing. The density of nc-Si grains is about 10¹¹cm^-2 as shown by TEM photographs. Using capacitance－voltage (C－V) measurements we investigated the electrical characteristics of the sandwiched structures. The charge storage phenomenon of the nc-Si layer was observed from the shift of flat-band voltage (V_FB) in C－V curves at a high frequency (1 MHz). We estimated the density of nc-Si grains to be about 10¹¹cm^-2 from the shift value of V_FB, which is in agreement with the result of TEM photographs. At the same time, we found that the shift of V_FB increased with the increase of the applied constant dc voltage or the thickness of the nc-Si layer.     

TiO2/Al2O3薄膜的原子层沉积和光学性能分析

采用原子层沉积技术在熔石英和BK7玻璃基片上镀制了TiO2/Al2O3薄膜,沉积温度分别为110℃和280℃。利用X射线粉末衍射仪对膜层微观结构进行了分析研究,并在激光损伤平台上进行了抗激光损伤阈值测量。采用Nomarski微分干涉差显微镜和原子力显微镜对激光损伤后的形貌进行了观察分析。结果表明,采用原子层沉积技术镀制的TiO2/Al2O3增透膜的厚度均匀性较好,Φ50 mm样品的膜层厚度均匀性优于99%;光谱增透效果显著,在1 064 nm处的透过率〉99.8%;在熔石英和BK7基片上,TiO2/Al2O3薄膜在110℃时的激光损伤阈值分别为（6.73±0.47）J/cm2和（6.5±0.46）J/cm2,明显高于在280℃时的损伤阈值。     

Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory

The characteristics of hybrid gadolinium oxide nanocrystal (Gd₂O₃-NC) and gadolinium oxide charge trapping (Gd₂O₃-CT) memories were investigated with different Gd₂O₃ film thickness. By performing the rapid thermal annealing on Gd₂O₃ films with different thickness, the Gd₂O₃-NCs with the diameter of 6–9 nm for charge storage, surrounded by the amorphous Gd₂O₃ (α-Gd₂O₃) layer, were formed. The α-Gd₂O₃ layer was considered to be the charge trapping layer, resulting in the large memory window of Gd₂O₃-NC/CT memories with thick Gd₂O₃ film. The charge trapping energy level of the Gd₂O₃-NCs and α-Gd₂O₃ layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 10⁶ program/erase cycling operation, the memory with thin Gd₂O₃ film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd₂O₃ film suffered from a 30% charge loss because of the traps within the α-Gd₂O₃ layer. The Gd₂O₃ film thickness of 10 nm was optimized to exhibit superior performances of the Gd₂O₃-NC/CT memory, which can be applied into the nonvolatile memory.     

ZrO2薄膜残余应力实验研究

采用ZYGO MarkⅢ-GPI数字波面干涉仪对电子束蒸发方法制备的ZrO2薄膜中的残余应力进行了研究,讨论了沉积温度、沉积速率等工艺参量对ZrO2薄膜残余应力的影响。实验结果表明：随着沉积温度及沉积速率的升高,ZrO2薄膜中残余应力状态由张应力变为压应力,且压应力值随着沉积温度升高而增大。同时用X射线衍射技术测量分析了不同沉积条件下ZrO2薄膜的微结构组织,探讨了ZrO2薄膜微结构与其应力的对应关系。     

界面极化注极聚丙烯薄膜驻极体的电荷存储特性研究

本文报道一种基于双层介质界面极化机理的新型驻极体注极技术: 借助辅助层对PP薄膜进行注极. 采用表面电位测试方法考察了注极温度、注极电压对所获PP薄膜驻极体电荷存储性能的影响, 并利用热刺激放电技术研究了其高温电荷存储性能, 同时测试了PP薄膜驻极体在X和Y方向的静电场分布. 结果表明: 界面极化注极是一种比电晕注极更为优异的驻极体形成方法. 在一定温度下, 驻极体表面电位随注极电压的增加而增加, 而且两者呈线性关系, 这一结果与注极过程的电荷积聚方程的分析完全一致. 注极温度的影响研究表明, 在保持注极电压不变(注极电压范围为0.5–3.0 kV)的情况下, 温度低于75 ℃时, 温度的变化对于注极效果的影响不明显; 当注极温度大于75 ℃ 时, PP薄膜驻极体的表面电位随注极温度的增加而增加. 表面电位随时间的变化研究表明, PP薄膜驻极体具有良好的电荷存储稳定性. 对其表面电位分布的测试表明, 界面极化注极所形成的PP薄膜驻极体呈现均匀的静电场分布.     

厚度对非极性聚合物薄膜驻极体电荷储存及电荷动态特性的影响

以Du Pont公司的商用Teflon FEP A型薄膜为例，通过热脉冲技术、等温表面电位衰减测量和开路热刺激放电电流谱分析等实验结果，讨论了经常温和高温电晕充电后样品厚度对薄膜驻极体的沉积电荷密度、薄膜驻极体的内电场、体电导率以及电荷储存稳定性的影响.通过热脉冲技术组合电导率温度曲线的测量，研究了在不同温度条件下样品厚度对沉积电荷层的平均电荷重心移动的影响.结果表明：在充电参数一定的条件下，随着膜厚的降低，储存电荷密度上升，但电荷稳定性有所下降.因此，合理地调控薄膜厚度，可以有效地优化驻极体的电荷储存能 关键词： 厚度 驻极体 电荷储存能力 电荷稳定性     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.     

Structural study of TiO2 thin films by micro-Raman spectroscopy

The Raman spectroscopy method was used for structural characterization of TiO₂ thin films prepared by atomic layer deposition (ALD) and pulsed laser deposition (PLD) on fused silica and single-crystal silicon and sapphire substrates. Using ALD, anatase thin films were grown on silica and silicon substrates at temperatures 125–425 °C. At higher deposition temperatures, mixed anatase and rutile phases grew on these substrates. Post-growth annealing resulted in anatase-to-rutile phase transitions at 750 °C in the case of pure anatase films. The films that contained chlorine residues and were amorphous in their as-grown stage transformed into anatase phase at 400 °C and retained this phase even after annealing at 900 °C. On single crystal sapphire substrates, phase-pure rutile films were obtained by ALD at 425 °C and higher temperatures without additional annealing. Thin films that predominantly contained brookite phase were grown by PLD on silica substrates using rutile as a starting material.     

Atomic-layer-deposited Al_2O_3 and HfO_2 on InAlAs: A comparative study of interfacial and electrical characteristics

Al_2O_3 and HfO_2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition(ALD).The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy(AR-XPS).It is demonstrated that the Al_2O_3 layer can reduce interfacial oxidation and trap charge formation.The gate leakage current densities are 1.37×10~6 A/cm~2 and 3.22×10~6 A/cm~2 at+1V for the Al_2O_3/InAlAs and HfO_2/InAlAs MOS capacitors respectively.Compared with the HfO_2/InAlAs metal-oxide-semiconductor(MOS) capacitor,the Al_2O_3/InAlAS MOS capacitor exhibits good electrical properties in reducing gate leakage current,narrowing down the hysteresis loop,shrinking stretch-out of the C-V characteristics,and significantly reducing the oxide trapped charge(Q_(ot)) value and the interface state density(D_(it)).     

Enhanced memory performance by tailoring the microstructural evolution of (ZrO2)0.6(SiO2)0.4 charge trapping layer in the nanocrystallites-based charge trap flash memory cells

ZrO₂ nanocrystallites based charge trap memory cells by incorporating a (ZrO₂)_0.6(SiO₂)_0.4 film as a charge trapping layer and amorphous Al₂O₃ as tunneling and blocking layer were prepared and investigated. The precipitation reaction in charge trapping layer forming ZrO₂ nanocrystallites during rapid thermal annealing was investigated by transmission electron microscopy. The density and size of ZrO₂ nanocrystallites are the critical factors for controlling the charge storage characteristics. The ZrO₂ nanocrystallites based memory cells after postannealing at 800 ^°C for 60 s exhibit the best electrical characteristics and a low charge loss ～5 % after 10⁵ write/erase cycles operation.     

充电栅压对聚四氟乙烯多孔膜驻极体储电能力的影响

利用室温下栅控恒压电晕充电、热脉冲技术、开路热刺激放电电流谱以及对在充电过程中通过样品电流的监测等方法，系统地研究了充电栅压对具有开放性孔洞结构的聚四氟乙烯（PTFE）多孔膜储电能力的影响，并讨论了导致这类影响的电荷动力学特性和材料的微结构根源 .结果显示，过高的充电栅压会导致沉积电荷密度下降和电荷衰减加剧，不利于这类新结构 功能材料压电活性的提高及其热稳定性的改善.合理的优化充电条件能使负极性充电PTFE多 孔膜驻极体在有机聚合物材料中显示优异的储电能力及电荷稳定性，并改善其作为双极性空 间电荷型压电传 关键词： 聚四氟乙烯 驻极体 储电能力 多孔膜     

Atomic layer deposition of TiO2 and Al‐doped TiO2 films on Ir substrates for ultralow leakage currents

TiO₂ and Al‐doped TiO₂ (ATO) films were grown on Ir substrates by atomic layer deposition using O₃ as the oxygen source. With increasing O₃ feeding time, the crystalline structure of the TiO₂ films was transformed from anatase to rutile. Above an O₃ feeding time of 35 s, the films crystallized as only rutile due to the formation of IrO₂ layer at the interface. The TiO₂ and ATO films showed higher dielectric constants of 78 and 51, respectively. The films on Ir showed superior leakage properties compared to the films on Ru due to the high work‐function of Ir. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.     

Influences of different structures on the characteristics of H_2O-based and O_3-based La_xAl_yO films deposited by atomic layer deposition

H_2O-based and O_3-based La_xAl_yO nanolaminate films were deposited on Si substrates by atomic layer deposition(ALD). Structures and performances of the films were changed by different barrier layers. The effects of different structures on the electrical characteristics and physical properties of the La_xAl_yO films were studied. Chemical bonds in the La_xAl_yO films grown with different structures and different oxidants were also investigated with x-ray photoelectron spectroscopy(XPS). The preliminary testing results indicate that the La_xAl_yO films with different structures and different oxidants show different characteristics, including dielectric constant, equivalent oxide thickness(EOT), electrical properties, and stability.     

原子层沉积Al2O3/n-GaN MOS结构的电容特性

利用原子层沉积技术制备了具有圆形透明电 极的Ni/Au/Al₂O₃/n-GaN金属-氧化物-半导体结构, 研究了紫外光照对样品电容特性及深能级界面态的影响, 分析了非理想样品积累区电容随偏压增加而下降的物理起源. 在无光照情形下, 由于极长的电子发射时间与极慢的少数载流子热产生速率, 样品的室温电容-电压扫描曲线表现出典型的深耗尽行为, 且准费米能级之上占据深能级界面态的电子状态保持不变. 当器件受紫外光照射时, 半导体耗尽层内的光生空穴将复合准费米能级之上的深能级界面态电子, 同时还将与氧化层内部的深能级施主态反应. 非理想样品积累区电容的下降可归因于绝缘层漏电导的急剧增大, 其诱发机理可能是与氧化层内的缺陷态及界面质量有关的“charge-to-breakdown”过程. 关键词： 原子层沉积 2O₃/n-GaN')" href="#">Al₂O₃/n-GaN 金属-氧化物-半导体结构 电容特性