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1.
Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices 总被引:1,自引:0,他引:1
This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO2. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO2/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability. 相似文献
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Improvement of Atomic-Layer-Deposited Al2O3/GaAs Interface Property by Sulfuration and NH3 Thermal Nitridation 下载免费PDF全文
Fermi level pinning at the interface between high-h gate dielectric and GaAs induced by unstable native oxides is a major obstacle for high performance GaAs-based metal-oxide-semiconductor (MOS) devices. We demonstrate the improved Al2O3/GaAs interracial characteristics by (NH4)2S immersion and NH3 thermal pretreatment prior to A1203 deposition. X-ray photoelectron spectroscopy (XPS) analysis confirms that sulfuration of GaAs surface by (NH4 )2S solution can effectively reduce As-O bonds while Ga-O bonds and elemental As still exist at Al2O3 /GaAs interface. However, it is found that N incorporation during the further thermal nitridation on sulfurated GaAs can effectively suppress the native oxides and elemental As in the sequent deposition of Al2O3. Atomic force microscopy (AFM) shows that the further thermal nitridation on sulfurated GaAs surface can also improve the surface roughness. 相似文献
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H/Al共掺杂对ZnO基透明导电薄膜光电性质和晶体结构的影响 总被引:1,自引:0,他引:1
利用H在ZnO中作为浅施主杂质的特性,研究了H掺杂对ZnO:Al透明导电薄膜特性的影响。通过降低ZnO:Al中Al的含量并同时引入H掺杂,解决了透明导电薄膜中高导电性与高透过率之间的矛盾。H的掺杂可以显著降低ZnO基透明导电薄膜的电阻率,这是由于H一方面作为施主可以提供电子从而提高了自由载流子浓度;另一方面与ZnO晶界中的O-结合降低了晶界势垒,提高了载流子迁移率。利用H掺杂,可以在Al掺杂量降低10倍的情况下,仍然能获得低电阻率(6.3×10-4 Ω·cm)的透明导电薄膜,同时其近红外波段(1 200 nm)透光率从64%提高到90%。这种具有高导电性和高透光性的透明导电薄膜可以应用于各类薄膜太阳能电池中以提升器件效率。 相似文献
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Ming-Kwei Lee Chih-Feng Yen 《Applied Physics A: Materials Science & Processing》2014,116(4):2051-2056
The (NH4)2S treatment can reduce native oxides and passivate GaAs. Atomic layer-deposited Al2O3 can further remove the residue native oxides by self-cleaning. Stacked with high dielectric constant TiO2 prepared by atomic layer deposition on Al2O3/(NH4)2S-treated GaAs MOS capacitor, the leakage current densities can reach 4.5 × 10?8 and 3.4 × 10?6 A/cm2 at ±2 MV/cm. The net effective dielectric constant of the entire stack is 18 and the interface state density is about 4.2 × 1011/cm2/eV. The fabricated enhancement-mode n-channel GaAs MOSFET exhibited good electrical characteristics with a maximum g m of 122 mS/mm and electron mobility of 226 cm2/V s. 相似文献
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C. Merckling Y.C. Chang C.Y. Lu J. Penaud G. Brammertz M. Scarrozza G. Pourtois J. Kwo M. Hong J. Dekoster M. Meuris M. Heyns M. Caymax 《Surface science》2011,605(19-20):1778-1783
The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III–V in CMOS is the electrical passivation of the interface with the high-κ gate dielectric. In this work, we show that in situ H2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III–V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III–V surfaces for CMOS applications. 相似文献
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《Chinese Journal of Physics (Taipei)》2018,56(4):1781-1788
Al/ZnO: Al heterojunction was fabricated by depositing ZnO: Al film on Al substrate by spray pyrolysis technique at 220 °C substrate temperature. XRD, SEM and EDAX techniques were used to study the properties of thin films. Heterojunction properties were studied by I–V and C–V measurements. The fabricated Al/ZnO: Al junctions were rectifying in character. The room temperature ideality factors of Al/ZnO: Al junctions are found to vary from 2.56 to 5.45. The reverse saturation currents are 5.21 × 10−9, 1.35 × 10−6, 1.99 × 10−6, 9.99 × 10−7 and 1.02 × 10−7 A for Al/ZnO: Al junctions. Junction forward current depends on doping concentrations and temperature, whereas reverse saturation current remains independent for Al concentration. The built-in-potential calculated from capacitance for Al/ZnO: Al junctions are 2.74, 2.60, 2.0, 2.50 and 2.43 V corresponding to 1, 2, 3, 4 and 5 mol% of Al. X-ray diffraction study confirmed that the films are polycrystalline, orientated in (0 0 2) plane. Scanning electron microscopy study confirmed circular ring patterns with inside ribbon type structure for Al doped ZnO films. 相似文献
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采用直流磁控溅射的方法制备了Al/ZnO/Al纳米薄膜,并对薄膜分别在真空及空气中进行退火处理.利用X射线衍射仪(XRD)和物理性能测量仪(PPMS)分别对薄膜样品的结构和磁性进行了表征.XRD分析表明,不同的退火氛围对薄膜的微结构有着很大的影响.采用了一种新的修正方法对磁测量结果进行修正,计算了基底拟合误差的最大值,并对修正后样品的磁性进行了分析.结果显示,室温铁磁性可能与Al和ZnO基体之间发生的电荷转移以及在不同退火氛围下Al在ZnO晶格中的地位变化有关.
关键词:
Al/ZnO/Al薄膜
铁磁性
磁性表征 相似文献
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采用电感耦合等离子体增强物理气相沉积法制备了(Cu,Al)掺杂ZnO薄膜,超导量子干涉磁强计测试结果表明,薄膜具有室温的铁磁性。采用激光共聚焦拉曼(Raman)光谱研究了(Cu,Al)掺杂ZnO薄膜的表面特性,以两种处理方式对薄膜进行了Raman光谱测试:共聚焦模式从薄膜表面开始至不同深度处进行测试;对薄膜样品进行预处理加工,采用面扫描模式在薄膜平面对(Cu,Al)掺杂ZnO薄膜的斜面进行测试。分析了Raman光谱A1(LO)峰的中心位置和强度变化,结果表明,界面处晶格应力和缺陷明显增强。这些晶格畸变和点缺陷的存在会对体系的铁磁性有促进作用。 相似文献
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利用物理气相沉积设备制备了Al/ZnO:Al薄膜样品,研究了该薄膜结构的发光特性。结果表明,在ZnO:Al薄膜表面镀一层Al岛薄膜可以增强其带边荧光,同时在475 nm附近产生蓝光峰。通过在Al岛薄膜和ZnO:Al薄膜之间引入一层5 nm的Ta2O5绝缘层可以使ZnO:Al薄膜的带边荧光和蓝光显著增强,并随着Ta2O5绝缘层厚度的增大而减弱。通过对Al/ZnO:Al样品进行退火处理可以使带边荧光和蓝光峰分别增强9倍和83倍。基于局域表面等离子体共振理论,计算了Al/ZnO:Al纳米结构的光学散射和吸收截面曲线。实验结果与理论计算相一致。 相似文献
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为了制备ZnO释能电阻并研究Al掺杂浓度对ZnO释能电阻材料的影响,通过改进的制陶工艺制备了不同Al掺杂浓度的ZnO导电陶瓷。实验结果表明,Al掺杂浓度对ZnO释能电阻的导电性、能量密度和线性度均有较大的影响。Al的掺杂能较好地改善ZnO释能电阻的线性度,非线性系数可低至1.02;Al掺杂能很好地控制ZnO的电阻率,使其达到0.54 Ω·cm;Al掺杂还能较好地改善ZnO陶瓷的均匀性和密度,从而提高ZnO释能电阻的能量吸收密度,能量吸收密度高达720 J/cm3,较金属释能材料高出2~3倍。 相似文献
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We report a transmission electron microscope study of the morphology and interfacial structure of Aluminium grown on (001) GaAs by chemical beam epitaxy (CBE). The Al grows in islands for all thicknesses deposited, and exhibits four distinct orientation relationships with respect to the substrate. One of these orientation relationships becomes dominant as growth progresses, with (011)Al parallel to (001)GaAs. Misfit dislocations can be seen in the interface between this orientation and the substrate with Burgers vector 1/4(110)GaAs, and a crystallographic analysis shows that these dislocations are associated with interfacial steps of height 1/2[001]GaAs. In (001)Al on (001)GaAs, the existence of these dislocations has in the past been regarded as evidence for the existence of a rigid-body shift of the Al in the interfacial plane. Using cross-sectional high-resolution TEM, it is shown that this shift is not present in the (011) orientation. The similarity in the microstructure and crystallography of the (001) and (011) orientations leads us to suggest that there is also no shift in (001) Al on (001)GaAs. This is in conflict with previous investigations of this system using a wide variety of techniques. 相似文献
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《Current Applied Physics》2010,10(3):761-765
The forward bias current–voltage (I–V) characteristics of Al/Rhodamine-101/n-GaAs structure have been investigated in the temperature range of 80–350 K. It has been seen a decrease in ideality factor (n) and an increase in the zero-bias barrier height (BH) with an increase in temperature. It has been seen that such a behavior of the BH and n obey Gaussian distribution of the BHs due to the BH inhomogeneities at the metal/semiconductor (MS) interface. The very strong temperature dependence of ideality factor of the structure has shown that the current processes occurring in the organic layer at the MS interface would be a possible candidate such as trap-charge limited conduction in determining the current at the intermediate and high bias regimes. Furthermore, it has been show that the Rh101 can be used to vary effective BHs for the metal/GaAs Schottky diodes. As a result, it has been determined that the BH value for conventional Al/n-GaAs SBD is remarkably higher than our own values of 0.68 eV obtained for the Al/Rh101/n-GaAs at 290 K. 相似文献
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Thin Al films with a thickness of 20-30nm were prepared by ultra-high vacuum deposition of Al onto a graphite surface parallel to a (0001) basal plane. The samples were annealed up to 1070K. X-ray photoelectron spectroscopy analysis has shown that for temperatures just higher than 770K, a little carbide occurs in the Al film and only an Al-C phase is present at the Al/graphite interface. After annealing at 970K, the Al4C3 phase can be observed, and the binding energy of the Al2p electrons increases continuously from 72.7 to 74.2eV with increasing temperature up to 1070K. Auger electron spectroscopy depth profiles are measured to investigate the phases existing in the Al film as well as at the Al/graphite interface. It is found that the Al4C3 phase at the interface is the final product of a series of Al carbides from the interfacial reaction between Al and graphite. 相似文献
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Comparative study of electrical characteristics for n-type 4H–SiC planar and trench MOS capacitors annealed in ambient NO 下载免费PDF全文
The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal–oxide–semiconductor(MOS) capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states.These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the(1120) and(1100) faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the(0001) face under the same NO annealing condition. In addition, it is found that Fowler–Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device.However, Poole–Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO_2/Si C interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO_2/Si C interfaces. 相似文献
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运用基于第一性原理的平面波贋势法,计算研究了Al (111)/Al_3Li (111)的界面性质.结果表明:Al (111)/Al_3Li (111)的界面具有三种原子配位关系结构,其中界面处仍保持与基体Al一致的三明治堆垛构型的界面稳定性最好.计算表明,该结构界面最薄弱层,位于Al_3Li (111)内,其分离功最小(约1.53 J/m~2),强度最弱,而基体Al和Al_3Li内部的强度随着到界面距离的增大而逐渐增强. 相似文献
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Wet thermal annealing effect on TaN/HfO2/Ge metal-oxide-semiconductor capacitors with and without a GeO2 passivation layer 下载免费PDF全文
Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor(MOS) structures with and without a GeO2 passivation layer are investigated.The physical and the electrical properties are characterized by X-ray photoemission spectroscopy,high-resolution transmission electron microscopy,capacitance-voltage(C-V) and current-voltage characteristics.It is demonstrated that wet thermal annealing at relatively higher temperature such as 550℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2,which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors.However,wet thermal annealing at 400℃ can decrease the GeO x interlayer thickness at the HfO2/Ge interface,resulting in a significant reduction of the interface states and a smaller effective oxide thickness,along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeO x in the wet ambient.The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C-V characteristics for the as-prepared HfO2 gated Ge MOS capacitors,but it also dissembles the benefits of wet thermal annealing to a certain extent. 相似文献
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基于密度泛函理论框架下的第一性原理平面波超软赝势方法, 构建了未掺杂与相同掺杂浓度的Zn1-xTMxO (TM=Al, Ga, In) 超胞模型,分别对模型进行了几何结构优化、态密度分布和能带分布的计算. 结果表明, 分别高掺杂 (Al, Ga, In) 相同原子分数3.125 at%的条件下, In掺杂对ZnO导电性能最好的结果, 计算结果和实验结果相一致.
关键词:
(Al,Ga,In) 高掺ZnO
导电性能
第一性原理 相似文献