Hot-carrier-induced MOSFET degradation under AC stress

The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.     

Hot-carrier-induced degradation in p-MOSFETs under AC stress

Lifetimes under AC stress are calculated with a quasistatic model using parameters extracted from DC stress data. For inverter-like waveforms, the measurement data show reasonable agreement with the simulation results. For waveforms with turnoff transient occurring in the presence of high drain voltage, more degradation than the model predicts is found if the transient is short (⩽10 ns) and gate voltage is high     

Retarding effect of surface base compensation on degradation of noise characteristics of BiCMOS BJTs

Hot carrier degradation of 1/f noise characteristics of bipolar junction transistors is found to be substantially reduced by arsenic surface compensation of the base region, in agreement with former reports on the improvement in reliability of such devices, inferred from their static characteristics studies.     

GIDL current degradation in LDD nMOSFET under hot hole stress

The degradation of gate-induced drain leakage（GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter I_DIFF.I_DIFF is the difference of GIDL currents measured under two conditions of drain voltage V_D=1.4 V and gate voltage V_G=-1.4 V while V_DG is fixed.After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region.These trapped holes diminishΔE_X which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make I_DIFF lessening.I_DIFF extracted from GIDL currents decreases with increasing stress time t.The degradation shifts of I_DIFF,MAX(ΔI_DIFF,MAX) follows a power law against t:ΔI_DIFF,MAX∝t^m, m= 0.3.Hot electron stress is performed to validate the related mechanism.     

热空穴应力下LDD nMOSFET中GIDL电流退化特性研究*

本文通过GIDL电流参数IDIFF对空穴应力下LDD nMOSFET中的GIDL电流退化进行了深入研究。IDIFF是在相同VDG下漏电压VD=1.4V和栅电压VG=-1.4V两种情形下的GIDL电流之差。空穴陷落在栅漏交叠区的氧化层中导致GIDL电流退化。这些陷落的空穴减小了上述两种对称的测试情形下的横向电场差ΔEX从而使得IDIFF表小。从GIDL电流中提取的IDIFF随着应力时间t的增加而减小。IDIFF的退化量ΔIDIFF,MAX与应力时间成幂指数关系：ΔIDIFF,MAX∝tm, m=0.3. 并用热电子应力实验验证了HHS实验中的相关物理机理。     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

双外延基区4H-SiC BJTs的高温特性研究

基于4H-SiC的材料特性及双外延基区BJTs的工作原理,依据漂移扩散及复合理论,求解在考虑4种复合机制下的双极晶体管直流增益,并通过二维仿真模型对其在高温条件下的工作特性进行了计算分析。结果表明,随着温度的升高,基区离化率的增加会导致发射极注入效率下降,从而降低器件的直流增益。同时,SiC/SiO2 界面态及钝化层的质量会影响器件的表面复合速度,从而造成大电流下直流增益的显著下降。     

High temperature characterization of double base epilayer 4H-SiC BJTs

Based on the material characteristics and the operational principle of the double base epilayer BJTs, and according to the drift-diffusion and the carrier recombination theory, the common emitter current gain is calculated considering four recombination processes. Then its performance is analyzed under high temperature conditions. The results show that the emitter injection efficiency decreases due to an increase in the base ionization rate with increasing temperature. Meanwhile, the SiC/SiO2 interface states and the quality of the passivation layer will affect the surface recombination velocity, and make an obvious current gain fall-off at a high collector current.     

Physically based comparison of hot-carrier-induced andionizing-radiation-induced degradation in BJTs

A physically based comparison between hot-carrier and ionizing radiation stress in BJTs is presented. Although both types of stress lead to qualitatively similar changes in the current gain of the device, the physical mechanisms responsible for the degradation are quite different. In the case of hot-carrier stress the damage is localized near the emitter-base junction, which causes the excess base current to have an ideality factor of two. For ionizing radiation stress, the damage occurs along all oxide-silicon interfaces, which causes the excess base current to have an ideality factor between one and two for low total doses of ionizing radiation, but an ideality factor of two for large total doses. The different physical mechanisms that apply for each type of stress imply that improvement in resistance to one type of stress does not necessarily imply improvement in resistance to the other type of stress. Based on the physical model, implications for correlating and comparing hot-carrier-induced and ionizing-radiation-induced damage are discussed     

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.     

Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested     

Electromigration under time-varying current stress

Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local V_CC and V_SS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.     

Tunnel oxide degradation under pulsed stress

A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness limited by the higher gate leakage current (Stress Induced Leakage Current, SILC) after cycling. It is possible to reduce the oxide degradation during cycling by reducing the stress pulse duration and increase the time between pulses. This allows the annealing of precursor sites with an overall reduction of stable traps. Aim of this work is the investigation of the SILC induced by pulsed stress and the corresponding charge trapped in the oxide during stress. The impact of the oxidation technology will also be discussed.     

Leakage current degradation in n-MOSFETs due to hot-electron stress

The field-induced drain-leakage current can become significant in NMOS devices with thin gate oxides. This leakage current component is found to be more prominent in devices with gate-drain overlap and can increase considerably with hot-electron stress. A method which shows how measuring the gate voltage needed to obtain a constant leakage value of 0.1 nA can yield useful information on the interface charge trap density is discussed     

Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

A deep analysis of the intrinsic junction and surface currents in power vertically diffused MOS devices with sub-micrometer channel length and thin gate oxide has been carried on after a typical reliability high temperature reverse bias (HTRB) stress. A reference set of gated diodes has also been examined in order to better understand the onset and evolution of post-stress leakage degradation. A comparison among complete MOSs, single body diodes and enriched diodes allows to highlight the role played by the point defectivity both at gate interface and in the bulk silicon close to the junction surface. We found that the typical interface defects involved in the leakage degradation are shallow traps and can be de-populated simply by a thermally activated mechanism. More specifically, the main degradation mechanism relies to band-defect-band tunneling localized at the surface drain/body junction where an intrinsic n-i-p region evolves due to a bird’s beak lateral profile of the body diffusion. We have demonstrated that the most important contribution to the activation of the precursor defect sites is given by the transverse electrical field that develops just below the SiO₂/Si interface within the n-i-p region during the stress.     

A physically based base pushout model for submicrometer BJTs in thepresence of velocity overshoot

By using a two-dimensional relaxation time approximation device simulator, base pushout phenomena for submicrometer bipolar junction transistors (BJTs) are analyzed. From the numerical analysis, it was clarified that, under the base pushout condition, the electron velocity exceeds the saturation velocity in most of the epi-collector region. Considering this velocity overshoot effect with two-dimensional carrier behavior, a base pushout model was developed. This model is applicable to the BJT equivalent circuit model. The model utility was verified for a 0.8 μm emitter-width BIT, and excellent agreement with measured I-V characteristics was obtained over wide injection conditions. Scaling effects on the velocity overshoot are also calculated, based on the constant current scaling. It is shown that the base pushout is suppressed due to the increased velocity overshoot level as the device sizes are scaled down     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Geometrical effects in high current gain 1100-V 4H-SiC BJTs

This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain /spl beta/=64 and a breakdown voltage of 1100 V. The high /spl beta/ value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on /spl beta/. A minimum distance of 2-3 /spl mu/m between the emitter edge and base contact implant was found adequate to avoid a substantial /spl beta/ reduction.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.