Charge-transfer complex modified bottom electrodes for high performance low voltage organic field-effect transistors and circuits

By using charge transfer complex silver and 2,3-dichloro-5,6-dicyano-p-benzoquinone (AgDDQ) modified silver as the bottom contact source/drain electrodes, high performance organic transistors and complementary inverter circuits using dinaphtho[2,3-b:2′,3’-f]thieno[3,2-b]thiophene (DNTT) as P-type organic semiconductors and N,N’-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) as N-type organic semiconductors were demonstrated. Devices with Ag-DDQ bottom contact electrodes exhibit good compatibility for both P and N-type organic semiconductors, the transistors and inverters exhibit excellent stability after storing in air ambient for more than 40 days. The fabrication process is compatible with photolithography technology, which is applicable for large area integrated circuits. All these results indicate the potential application of Ag-DDQ modified electrodes in all-organic, flexible, and low-power electronics.     

低电压下CMOS数字电路概率模型研究

为解决数字电路低功耗问题,电路工作电压被不断降低,导致电路逻辑器件呈现概率特性。本文提出了低电压下CMOS数字电路的错误概率模型,并完成硬件电路测试验证。本文首先详述了深亚微米（DSM）量级的门电路及模块在低电压供电条件下导致器件出错的因素,结合概率器件结构模型推导基本逻辑门概率模型,并提出了状态转移法用于完成由门级到模块级的概率分析模型;我们搭建硬件平台对CMOS逻辑芯片进行了低供电压测试,通过分析理论推导结果与实测结果,验证并完善了分析模型。实验结果表明,由状态转移法推导的电路概率模型符合电路实际性能,从而为构建低电压下数字电路概率模型提供了可靠分析模型。      

A high performance RDS-detector for low voltage applications

The design and realisation of the analog part for an RDS-receiver, the RDS-detector, is discussed in this paper. The RDS-receiver is developed towards low voltage applications (1.8 V) with low power consumption requirements. A new topology for RDS-receivers is introduced resulting in an important quality improvement, mainly being a higher phase-linearity and a lower power consumption. The performance of the chip is compared to existing RDS-receivers. These receivers use an analog integrated bandpass filter. In the presented topology direct conversion followed by lowpass filtering is used. The chip is realised in a fully differential switched-capacitor technique with correlated double sampling. The latter is used to obtain a very low equivalent input DC-offset. The chip is implemented in a 2µm BiCMOS technology.     

Ultra low power DG FinFET based voltage controlled oscillator circuits

Voltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.     

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 μm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/μm². The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.     

A mixed CMOS-DMOS-JFET technology for switching circuits with high voltage output stages

This paper describes the development of a technology that incorporates low voltage CMOS and high voltage JFET and DMOS transistors on the same chip. The fabrication sequence is based on a metal gate CMOS process. The influence of the process variables and trade-offs in the characteristics of the devices have been discussed. The successful application of the technology to a thermal printer head driver circuit has been demonstrated.     

Reliability issues in 650V high voltage bipolar-CMOS-DMOS integrated circuits

Dominant failure modes in high power/high voltage (650V) BCD-technologies are threshold voltage instabilities of the lateral DMOS transistor due to sodium ingression and parasitic leakage currents in low voltage devices induced by high surface potentials originating from the high voltage devices. The failure mechanisms and their temperature dependence have been characterized and process and layout improvements are demonstrated.     

A low distortion bipolar mixer for low voltage direct up-conversionand high IF systems

This paper describes the implementation of a low distortion mixer for direct up-conversion and high IF systems. A Gilbert cell with a low distortion transconductance constitutes the mixer core. A current feedback loop is used to linearize the transconductance stage, achieving an alternate channel leakage of -71 dBc with a power penalty of 15%. The mixer operates from 2.7 to 7.5 V of supply voltage and over a temperature range of -40 to 85°C. It provides -3 dBm output power while drawing 7.5 mW from a 3-V supply. The mixer is implemented in 1-μm BiCMOS for a global system for mobile communications (GSM) chip set     

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm², a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming     

On-chip high voltage charge pump in standard low voltage CMOS process

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 /spl mu/m CMOS process is presented. For a 250 k/spl Omega/ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed     

低电压高效整流器在能量收集系统中的应用

提出了一种应用在能量收集系统中的低电压CMOS全波整流器。通过引入比较器控制开关,在0.18微米工艺下,最低工作电压可以小于0.7V。由于只使用一个比较器,大大缩减了芯片成本。与相关研究成果比较,设计采用非对称结构,电压转换效率高达93%,系统能量效率达到83%。     

一种全集成高电源抑制比的低压差线性稳压器

This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC （Shanghai, China）. Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO＇s active chip-area is only smaller than 0.02 mm2.     

应用于低功耗型专用集成电路的超低功耗高电源抑制比电压基准源

介绍一种超低功耗、无片上电阻的带隙基准源。该带隙基准源主要用于低功耗型专用集成电路。采用Oguey电流源结构来减小静态电流,以降低功耗;采用共源共栅电流镜以提高电源电压抑制比和电压调整率。电路基于SMIC 0.18-μm CMOS工艺进行设计并流片。测试结果表明,在温度范围25℃-100℃内,温漂系数为66 ppm/℃,电源电压范围为1.8V - 3.3V时,电压调整率为0.9%,在100 Hz时,电源电压抑制比为-49 dB。电路功耗仅为200 nW,芯片面积为0.01 mm2。该电路可作为低功耗专用集成电路里的基本模块。     

低压工作的高速10bit Pipelined ADC

本文提出了一种低压工作的高速1Obit Pipelined ADC。采用自举时钟采样和Cascode频率补偿等方法,该ADC可以在低电压下工作,并达到较高的带宽。该ADC在HJTC 0.18-μm CMOS数模混合工艺下进行了设计仿真和流片测试,结果表明：当供电电压为1．8V,采样频率为62．5MSample／s时,所设计的ADC对于1MHz的输入信号转换有效位数可以达到52．2dB SFDR、44．8dB SNR和44．3dB SNDR。     

New redundant logic design concept for high noise and low voltage scenarios

This paper presents a new redundant logic design concept named Turtle Logic (TL). It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two's complement 8×8-bit pipelined Baugh–Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0% errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes.     

Wideband high dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications

A high frequency CMOS variable gain amplifier (VGA) employing a new gain stage cell is proposed. A design technique based on the proposed VGA enables enhancement of its operating frequency up to about 350 MHz with a gain control range of 84 dB. The power consumption of the VGA implemented using a 0.18 /spl mu/m CMOS standard process is about 3 mA at 1.8 V supply voltage.