High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Local structure around Zn and Ga in solution‐processed In–Ga–Zn–O and implications for electronic properties

We study by X‐ray absorption spectroscopy the local structure around Zn and Ga in solution‐processed In–Ga–Zn–O thin films as a function of thermal annealing. Zn and Ga environments are amorphous up to 450 °C. At 200 °C and 450 °C, the Ga atoms are in a β‐Ga₂O₃ like structure, mostly tetrahedral gallium oxide phase. Above 300 °C, the Zn atoms are in a tetrahedral ZnO phase for atoms inside the nanoclusters. The observed formation of the inorganic structure above 300 °C may be correlated to the rise of the mobility for IGZO TFTs. The Zn atoms localized at the nanocluster boundary are undercoordinated with O. Such ZnO cluster boundary could be responsible for electronic defect levels. Such defect levels were put in evidence in the upper half of the band gap. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Electrical in‐situ characterisation of interface stabilised organic thin‐film transistors

We report on the electrical in‐situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom‐gate/bottom‐contact (coplanar) configuration are electrically characterised in‐situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO₂ with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor param‐ eters is studied on a bi‐layer dielectric of a 150 nm of SiO₂ and 20 nm of poly((±)endo,exo‐bicyclo[2.2.1]hept‐5‐ene‐2,3‐dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO₂ dielectric. The thin layer of PNDPE, which is an intrinsically photo‐patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Flexible InGaZnO thin film transistors using stacked Y2O3/TiO2/Y2O3 gate dielectrics grown at room temperature

In this Letter, we report a low operation voltage and high mobility flexible InGaZnO thin‐film transistor (TFT) using room‐temperature processed Y₂O₃/TiO₂/Y₂O₃ gate dielectric. The flexible IGZO TFT showed a low threshold voltage of 0.75 V, a small sub‐threshold swing of 137 mV/decade, a good field effect mobility of 32.7 cm²/V s, and a large I_on/I_off ratio of 1.7 × 10⁶. The low operation voltage, small sub‐threshold swing and high mobility could be ascribed to the combination of high‐κ TiO₂ and large band gap Y₂O₃, which provide the potential to meet the requirements of low‐temperature and low‐power portable electronics.

     

One decade of fully transparent oxide thin‐film transistors: fabrication,performance and stability

We review the history of fully transparent oxide thin‐film transistors. Their performance and stability increased during the past ten years of their existence, thus enabling the design of novel applications in transparent electronics. However, certain disadvantages of the well established leading technology of metal–insulator–semiconductor field‐effect transistors (MISFETs), adapted from the silicon‐based complementary metal–oxide–semiconductor (CMOS) and thin‐film transistor technology, may be overcome by alternative transistor designs like metal–semiconductor field‐effect transistors (MESFETs). We compare the stability of published transparent MISFET with our transparent MESFET (TMESFET) technology against bias stress, towards illumination, at elevated temperatures and long‐term stability.

     

Influence of polymer dielectric surface energy on thin‐film transistor performance of solution‐processed triethylsilylethynyl anthradithiophene (TES‐ADT)

This study investigates the correlation between surface energy of polymer dielectrics and the film morphology, microstructure, and thin‐film transistor performance of solution‐processed 5,11‐bis(triethylsilylethynyl) anthradithiophene (TES‐ADT) films. The low surface energy polyimide (PI) dielectric induced large grains with strong X‐ray reflections for spin‐cast TES‐ADT films in comparison to high surface en‐ ergy poly(4‐vinyl phenol) (PVP) dielectric. Furthermore, thin‐film transistors based on spin‐cast TES‐ADT films on PI dielectric exhibited enhanced electrical performance, small hysteresis, and high stability under bias stress with carrier mobility as high as 0.43 cm²/Vs and a current on/off ratio of 10⁷. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Fabrication of 6,13‐bis(triisopropyl‐silylethynyl)–pentacene thin‐film transistors with the silver ink transfer method using a polymer stamp

We fabricated 6,13‐bis(triisopropylsilylethynyl)–pentacene (TIPS–pentacene) thin film transistors using a direct metal transfer method. Using different metals, such as Au and Ag ink, electrode patterns are formed from the relief region of the polymer mold. TIPS–pentacene TFTs using the Ag ink transfer method show a similar performance to those using the Au metal transfer method. This method has advantages over the Au metal transfer method because it does not require vacuum equipment and a dry etching process. The self‐assembled monolayer (SAM) treated device exhibits a carrier mobility of 9.5 × 10^–2 cm²/V · s, and an on/off ratio of 4.6 × 10⁴. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Organic thin‐film transistor fabricated between flexible films by thermal lamination

We propose a novel and complementary method for fabrication of flexible electronics. This method is not based on conventional printing using inks, but is based on the application of a toner‐based method such as Xerox or laser printing, followed by a lamination process. The lamination method is a solvent‐free and material‐saving process that simultaneously seals the devices, and the fabricated flexible devices have structural durability against bending. We have also shown that thermal lamination has an oriented growth effect, and the electrical characteristics of flexible organic field‐effect transistors did not degrade under a bending radius of 1 mm.

     

P‐type tin‐oxide thin film transistors for blue‐light detection application

We reported the characteristics of p‐type tin‐oxide (SnO) thin film transistors (TFTs) upon illumination with visible light. Our p‐type TFT device using the SnO film as the active channel layer exhibits high sensitivity toward the blue‐light with a high light/dark read current ratio (I_light/I_dark) of 8.2 × 10³ at a very low driven voltage of <3 V. Since sensing of blue‐light radiation is very critical to our eyes, the proposed p‐type SnO TFTs with high sensitivity toward the blue‐light show great potential for future blue‐light detection applications.

     

High‐mobility pentacene OTFT with TaLaO gate dielectric passivated by fluorine plasma

Pentacene thin‐film transistor with high‐κ TaLaO as gate dielectric has been fabricated and shows a carrier mobility of 0.73 cm²/V s, much higher than that based on pure La₂O₃ (0.43 cm²/V s) due to the smoother surface of the TaLaO film and thus larger pentacene islands grown on it in the initial stage. Moreover, among various times for fluorine‐plasma treatment on the TaLaO gate dielectric, 100 seconds result in the highest carrier mobility of 1.12 cm²/V s due to (1) smoothest oxide surface achieved by fluorine passivation of oxide traps, as measured by AFM and supported by smallest sub‐threshold swing and lowest low‐frequency noise; (2) the largest pentacene grains grown on the smoothest oxide surface, as demonstrated by AFM.

     

In–Ga–Zn–O MESFET with transparent amorphous Ru–Si–O Schottky barrier

Rectifying transparent amorphous Ru–Si–O Schottky contacts to In–Ga–Zn–O have been fabricated by means of reactive sputtering without any annealing processes nor semiconductor surface treatments. The ideality factor, effective Schottky barrier height and rectification ratio are equal to 1.6, 0.9 eV and 10⁵ A/A, respectively. Ru–Si–O/In–Ga–Zn–O Schottky barriers were employed as gate electrodes for In–Ga–Zn–O metal–semiconductor field‐effect transistors (MESFETs). MESFET devices exhibiting on‐to‐off current ratio at the level of 10³ A/A in a voltage range of 2 V, with subthreshold swing equal to 420 mV/dec were demonstrated. A channel mobility of 7.36 cm²/V s was achieved. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

N2O处理对背沟刻蚀金属氧化物薄膜晶体管性能的影响

通过采用稀土元素镨掺杂铟锡锌氧化物半导体作为薄膜晶体管沟道层,成功实现了基于铝酸的湿法背沟道刻蚀薄膜晶体管的制备.研究了N₂O等离子体处理对薄膜晶体管背沟道界面的影响,对其处理功率和时间对器件性能的影响做了具体研究.结果表明,在一定的功率和时间处理下能获得良好的器件性能,所制备的器件具有良好的正向偏压热稳定性和光照条件下负向偏压热稳定性.高分辨透射电镜结果显示,该非晶结构的金属氧化物半导体材料可以有效抵抗铝酸的刻蚀,未发现明显的成分偏析现象.进一步的X射线光电能谱测试表明, N₂O等离子体处理能在界面处形成一个富氧、低载流子浓度的界面层.其一方面可以有效抵抗器件在沉积氧化硅钝化层时等离子体对背沟道的损伤;另一方面作为氢的钝化体,抑制了低能级施主态氢的产生,为低成本、高效的薄膜晶体管性能优化方式提供了重要参考.