微电子封装技术的优势与应用

现阶段,电子封装技术在电子设备运用中发挥着非常重要的作用,特别是在电子器件功能集成以及布局优化等方面,发挥的作用日益重要,应用需求也大幅度加强。文章主要就微电子封装技术的优势与应用展开详细论述。     

微电子封装技术的发展与展望

微电子技术的发展,推动着微电子封装技术的不断发展、封装形式的不断出新。介绍了微电子封装的基本功能与层次,微电子坟技术发展的三个阶段,并综述了微电子封装技术的历史、现状、发展及展望。     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

电子封装用SiCp/Al复合材料的研究现状及展望

电子封装技术的快速发展对封装材料的性能提出了更为严格的要求。文章介绍了电子封装用SiCp/Al复合材料的研究现状和进展,讨论了其制备工艺和性能。文中着重介绍了空气气氛下的无压自浸渗制备方法,并进一步提出了SiCp/Al复合材料存在的主要问题以及今后的研究方向。     

硅通孔技术的发展与挑战

3D堆叠技术近年来发展迅速,采用硅通孔技术(TSV)是3D堆叠封装的主要趋势.介绍了3D堆叠集成电路、硅通孔互连技术的研究现状、TSV模型;同时阐述了TSV的关键技术与材料,比如工艺流程、通孔制作、通孔填充材料、键合技术等;最后分析了其可靠性以及面临的挑战.TSV技术已经成为微电子领域的热点,也是未来发展的必然趋势,运用它将会使电子产品获得高性能、低成本、低功耗和多功能性.     

PI/Cr钝化对提高AlGaN/GaN HEMTs 击穿电压的研究

A novel AlGaN/GaN high electric mobility transistor（HEMT） with polyimide（PI）/chromium（Cr） as thepassivationlayerisproposedforenhancingbreakdownvoltageanditsDCperformanceisalsoinvestigated.The Cr nanoparticles firstly introduced in PI thin films by the co-evaporation can be used to increase the permittivity of PI film. The high-permittivity PI/Cr passivation acting as field plate can suppress the fringing electric field peak at the drain-side edge of the gate electrode. This mechanism is demonstrated in accord with measured results. The experimental results show that in comparison with the AlGaN/GaN HEMTs without passivation, the breakdown voltage of HEMTs with the PI/Cr composite thin films can be significantly improved, from 122 to 248 V.     

一种新颖的Ka频段T/R组件立体混合集成封装

介绍了一种新颖的Ka频段T/R组件立体混合集成封装.针对Ka频段T/R组件高频率和高密度的特点,提出了一种新颖的多层组装和双面密封的立体电路结构,采用软基片、FR-4等简单成熟工艺,实现了Ka频段M- MCM的混合集成.该封装具有集成度高、散热性好和可靠性高等特点,能够应用于Ka频段二维有源相控阵T/R子阵的工程研制.     

Reflow and burn-in of a Sn-20In-0.8Cu ball grid array package with a Au/Ni/Cu pad

The intermetallic compounds formed after reflow and burn-in testing of a Sn-20In-0.8Cu solder ball grid array (BGA) package are investigated. Along with the formation of the Cu₆(Sn_0.78In_0.22)₅ precipitates (IM1) in the solder matrix, scallop-shaped intermetallic compounds (IM2) with a compositional mixture of Cu₆(Sn_0.87In_0.13)₅ and Ni₃(Sn_0.87In_0.13)₄ appear at the interfaces between the solder balls and Au/Ni/Cu pads. A significant number of intermetallic particles (IM3), with a composition of (Au_0.80Cu_0.20)(In_0.33Sn_0.67)₂, can also be found in the solder matrix. After aging at 115°C for 750 h, an additional intermetallic compound layer (IM4) with a composition of (Ni_0.91Cu_0.09)₃(Sn_0.77In_0.23)₂ is formed at the interface between IM2 and the Ni layer. The ball shear strength of the Sn-20In-0.8Cu BGA solder after reflow is 4.5 N and will rise to maximum values after aging at 75°C and 115°C for 100 h. With a further increase of the aging time at both temperatures, the joint strengths exhibit a tendency to decline linearly at about 1.7×10⁻³ N/h.     

A Graphene‐Based Vacuum Transistor with a High ON/OFF Current Ratio

A graphene‐based vacuum transistor (GVT) with a high ON/OFF current ratio is proposed and experimentally realized by employing electrically biased graphene as the electron emitter. The states of a GVT are switched by tuning the bias voltage applied to the graphene emitter with an ON/OFF current ratio up to 10⁶, a subthreshold slope of 120 mV dec^?1 and low working voltages of <10 V, exhibiting switching performances superior to those of previously reported graphene‐based solid‐state transistors. GVTs are fabricated and integrated using silicon microfabrication technology. A perfectly symmetric ambipolar device is achieved by integrating two GVTs, implying the potential of realizing vacuum integrated circuits based on GVTs. GVTs are expected to find applications in extreme environments such as high temperature and intense irradiation.     

Electromigration in aluminum/silicon/copper metallization due to the presence of a thin oxide layer

The effect of a thin layer of SiO₂ (50 nm) on the electromigration behavior of Al/ 0.8wt.%Si/0.5wt.%Cu metallization, passivated by spin-on-glass, phosphorus silicate glass and silicon nitride as part of the complementary metal oxide semiconductor technology fabrication process was studied. It is found that voids were formed along the edge of the metallization line as opposed to formation at triple point of grain boundaries. At the same stress current of 1 × 10⁶ A/cm², thicker metallization layer (600 nm) showed an improvement in median time to failure (MTF) (1.4 times) with smaller void size (0.2 to 0.4 μm) over one without an underlying oxide, whereas if the metallization thickness is thin (300 nm), the MTF is degraded (0.6 times) with larger void size formed (0.3 to 1.0 μm).     

Effect of temperature cycling on angular alignment in add/drop filter-module packaging

The thermally-induced, fiber-alignment shifts of ferrule-solder-ferrule (FSF) joints in add/drop filter-module packaging for multiplexer/demultiplexer applications have been studied experimentally and numerically. From experimental measurements of the module-insertion loss difference (0.3 dB) with and without temperature cycling, FSF angular-tilt misalignments of up to 0.05° were found after undergoing 42 temperature cycles. The effects of an imperfect soldering process along the two ferrules during the packaging of an add/drop filter module on the angular-tilt misalignment has been explored in this study. An elastic-plastic finite-element method (FEM) was performed to evaluate the variation of thermal stresses, the distribution of residual stresses, and the angular-tilt misalignment of the FSF joints. Experimental measurements of the FSF angular-tilt misalignment were in good agreement with the FEM calculations. The major angular-tilt misalignments of FSF joints in add/drop filter-module packaging during temperature cycling may come from the localized plastic-solder yielding introduced by the local thermal-stress variation and the redistribution of the residual stresses within the solder. The FSF angular-tilt misalignment and, hence, fiber-alignment shift of the add/drop filter module under temperature-cycling tests can be reduced significantly if a perfect soldering process along the two ferrules can be fabricated.     

掺Na制备柔性聚酰亚胺衬底CIGS薄膜太阳电池

研究了Na掺入对低温沉积柔性聚酰亚胺(PI)衬底Cu(In,Ga)Se2(CIGS)薄膜的结构和电学特性影响。研究结果表明:Na元素的掺入使Ga元素的扩散受到了阻滞,但对CIGS薄膜晶粒尺寸没有明显的影响,少量的Na可提高CIGS薄膜的载流子浓度和降低电阻率;Na的掺入可明显提高CIGS薄膜太阳电池的器件特性,通过优化掺Na工艺,制备的柔性PI衬底—CIGS薄膜太阳电池的最高转换效率达到10.4%。     

Pulsed electrodeposition of the eutectic Au/Sn solder for optoelectronic packaging

As an alternative to the time-consuming solder pastes and preforms currently being used, a method of electroplating the eutectic Au/Sn alloy has been developed. Using a pulsed co-deposition process, it is possible to plate the solder directly onto a wafer at or near the eutectic composition from a single solution. It has been shown that two distinct phase, Au₅Sn and AuSn, can be deposited separately over a range of current densities at compositions of 15 at. %Sn and 50 at. %Sn, respectively. by adjusting the deposition current pulse, it is possible to plate both phases in a layered composite thereby achieving any desired composition between 15 and 50 at. %Sn, including the commercially important eutectic composition.     

Intermetallic embrittlement of thin unsupported tin/copper specimens

Thin, unsupported vacuum-cast tin samples were prepared and, after half of the samples were coated with a thin layer of evaporated copper, stressed to failure using a specialized tensile testing apparatus. The samples were examined optically and by analytical scanning and transmission electron microscopy. Samples coated with copper exhibited very different mechanical behavior than did the uncoated tin samples which exhibited simple ductile behavior. Postfailure examination of the specimens shows that the differences in mechanical behavior are not due to the copper coating, but, in fact, due to copper-tin intermetallics formed within the bulk of the tin.     

金刚石/铜复合散热材料的制备和检测

金刚石/铜复合材料具有高的热导率和可调的热膨胀系数,是一种极具竞争力的新型电子封装材料,可作为散热材料广泛应用于高功率、高封装密度的器件中。文中从工程化的角度出发,对应用中的瓶颈因素进行了研究。为改善其钎焊性能,采用磁控溅射、电镀等方法在金刚石/铜表面获得了附着力、可焊性良好的Ti-Cu-Ni-Au复合膜层。在此基础上进行了钎焊试验,金锡焊料在复合膜层上铺展良好、无虚焊。对金刚石/铜的散热效果与钼铜片做了对比试验,结果表明,在相同条件下,与钼铜热沉片相比,降温幅度超过20℃,具有更优异的散热效果。     

SiC p／Al复合材料镀金工艺研究

对SiC体积分数高达60％以上的SiCp／A l金属基复合材料进行镀金工艺实验,工艺分步实施化学镀镍、热处理、电镀镍、电镀金步骤,得到的镀层表面光滑平整,没有明显的结瘤和夹杂,与基材的结合力强。该工艺作为SiC p／A l可焊性表面处理技术之一,兼具可接触导通、良好的焊接性能、能兼容各种助焊剂,对于铝基复合材料表面处理具有十分重要意义。     

纯铜表面激光熔覆TiB2/Cu涂层的组织及导电性能

为了满足电磁导轨的使用要求,采用激光熔覆技术在纯铜表面通过预置粉的方式制备了不同成分TiB2/Cu涂层,用光学显微镜、扫描电镜和X射线衍射分析了涂层的微观结构及相组成。涂层由Cu和TiB2两相组成,当TiB2的质量分数分别为0.02,0.05和0.1时,涂层的显微硬度分别约为95HV0.1,105HV0.1和152HV0.1,电导率为22.9MS/m,20.4MS/m和16.4MS/m。涂层与基体呈良好冶金结合,无裂纹在,TiB2颗粒存在团聚现象,熔覆层组织为外延生长的柱状晶。结果表明,随着TiB2的含量增大,涂层显微硬度升高,涂层的电导率下降。     

Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill,novel terminal pad structures,and processing optimization

Packaging of 90-nm Cu/Low-K chips presents a serious challenge, which requires an advanced ceramic flip chip solution. Finer Cu interconnects are expected to interact differently with the current underfill-to-die passivation stack-up structures used for Al or previous Cu technology nodes especially in system level applications. Furthermore, the more porous and brittle-proned advanced Low-K (K<3) dielectrics present additional process incompatibility problems such as stress-induced crackings and delaminations. These reliability issues in various stress-relieving passivation structures and materials (i.e., Benzocyclobutene (BCB) and single versus double SiOxNy passivations) have not been extensively studied. This study analyzes the effect of the eight metal layer 90-nm Cu/Low-K flip chip devices through designed experiments using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings: temperature cycling (TC), highly accelerated stress testing (HAST), and high-temperature storage (HTS). Black Diamond Low-K and HiCTE ceramic substrates are employed for the large package form factor. The active Si uses eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film-deposited under bump metallurgy (UBM). It is found that the double passivation pad structures are less susceptible to reliability damage for various types of underfills, although a single passivation with BCB coating combined with an optimal underfill can also yield a similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and the underfill interface failure mode mechanism are examined by functional testing, chemical deprocessings, scanning acoustic microscope (SAM), and scanning electron microscope (SEM)/energy-dispersive x-ray (EDX). The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/Low-K generations.     

90nm工艺及其相关技术

ITRS2001规划2004年实现90nm工艺,英特尔、AMD等世界顶级半导体公司将于2003年采用90nm工艺量产微处理器和逻辑器件。这样使ITRS2001整整提前了一年。90nm工艺包括193nm光刻技术、高k绝缘材料、高速多层铜互连技术、低k绝缘材料、应变硅技术和电压隔离技术等新技术。193nm光刻技术是实现90nm工艺达量产的最关键技术,为此,必须采用193nmArFstepper(准分子激光扫描分步投影光刻机)。讨论了90nm工艺达量产的难点,如掩模版成本较高、成品率较低和应用面暂时不宽等。     

一种Ku波段宽调谐范围高输出功率的InGaP/GaAs HBT VCO

本文介绍了一种采用InGaP/GaAs HBT工艺实现的全集成应用于Ku波段的压控振荡器(VCO)。该VCO采用Colpitts结构,以达到宽调谐范围,并且该VCO取得了较高的输出射频功率。测试结果表明：该VCO的振荡频率为12.82 GHz～14.97 GHz,调谐范围为15.47%,输出射频功率为0.31 dBm～6.46 dBm,在载频13.9 GHz处相位噪声为-94.9 dBc/Hz@1 MHz。在5 V单电源直流偏置下该VCO的功耗为52.75 mW,其芯片尺寸为0.81 mm×0.78 mm。最后,本文对VCO的品质因数FOM指标进行了讨论。