Hybrid delta-sigma ADC

A hybrid (analog/digital) architecture is proposed to implement a robust high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a scaling block and a high-order single-bit digital modulator. The combination simplifies the realization of the analog modulator, and it allows the use of most of its full-scale input range.     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC.The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage.Experimental results show that for a 1.25 MHz @ -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.     

A comparative analysis of parallel delta-sigma ADC architectures

Parallelism can be used to increase the conversion bandwidth of delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADCs). Time-interleaved, parallel /spl Delta//spl Sigma/, and frequency-band-decomposition ADCs are three parallel architectures that are shown to be explained using the same underlying theory. This common structure is then used to explore the design tradeoffs among these architectures. It is shown that the frequency-band-decomposition ADC is insensitive to channel mismatches but it is the most complex to design. The Hadamard modulated parallel /spl Delta//spl Sigma/ ADC provides the best performance (without considering nonidealities) but requires large digital filters. Finally, a randomization technique is described that can be used with parallel /spl Delta//spl Sigma/ architectures to spread out the tonal energy due to channel mismatches over the frequency spectrum.     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC(analog-to-digital converter) for wireless local area network standards is presented.A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted;however,this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR(signal to noise and distortion ratio),using 4-bit ADCs in both stages to minimize the quantization noise.Data weighted ...     

A continuous-time delta-sigma ADC for portable ultrasound scanners

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2 V, a bandwidth of 10 MHz and an oversampling ratio of 16 leading to an operating frequency of 320 MHz. The design occupies a die area of \(0.0175\hbox { mm}^2\). Simulations with extracted parasitics show a SNR of 45.2 dB and a current consumption of \(489 \,\upmu \hbox {A}\). However, by adding a model of the measurement setup used, the performance degrades to 42.1 dB. The measured SNR and current consumption are 41.6 dB and \(495\,\upmu \hbox {A}\), which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given.     

Ultra-low power incremental delta-sigma ADC for energy harvesting sensor applications

This paper presents an ultra-low power incremental \({\varDelta {\Sigma }}\) ADC with flexible sampling frequency, accuracy, and operational duty-cycle. The flexibility and low leakage power enable efficient scaling of average power together with performance. This allows simultaneous optimization of the sensor system (1) for various multiplexed, both on-chip and off-chip sensor interfaces, and (2) for a wide range of available harvested energy. The architecture allows further flexibility as it can be used in regular continuous \({\varDelta {\Sigma }}\) mode as well, without trading off accuracy. The ADC was implemented in a 180 nm CMOS process, on the same ASIC with a temperature sensor, pressure sensor and energy harvesting functionalities. The ADC has a nominal power consumption of \(1.3\,\upmu\)W, SNDR of 68 dB and BW of 200 Hz, denoting a \(FOM_w =1.58\) pJ/conv.     

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.     

Wideband cascade delta-sigma modulator with digital correction forfinite amplifier gain effects

The authors present an alternative approach to reducing the effects of finite amplifier open-loop gain in cascade delta-sigma modulators. The proposed gain compensation is carried out in the digital domain and thus requires no additional analogue circuitry. The method is illustrated by the example of a double third-order cascade circuit which, when properly compensated for finite gain effects, can yield 1-20 bit resolution with oversampling ratios as low as 16-24     

一种基于开关型运放和双向循环移位DWA的0.9V Delta-Sigma模数转换器

This paper presents a low-power high-precision switched-opamp(SO)-based delta-sigma(△Σ) analog-to -digital converter(ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit(FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.     

A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers

We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-/spl mu/m CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented.     

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet

In this work the design of a continuous-time ΔΣ modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5 MHz and 8, resulting in a clock frequency of 1 GHz. It was designed and implemented in a standard 90 nm CMOS technology. The active area of the modulator measures . It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8 mW from a nominal power supply of 1 V.     

A 12-mW ADC delta-sigma modulator with 80 dB of dynamic rangeintegrated in a single-chip Bluetooth transceiver

This paper presents a switched-capacitor multibit ADC delta-sigma modulator for baseband demodulation integrated in a single-chip Bluetooth radio-modem transceiver that achieves 77 dB of signal-to-noise-plus-distortion ratio (SINAD) and 80 dB of dynamic range over a 500-kHz bandwidth with a 32-MHz sample rate. The 1-mm² circuit is implemented in a 0.35-μm BiCMOS SOI process and consumes 4.4 mA of current from a 2.7-V supply     

A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS

A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.     

Design and Power Optimization of High-Speed Pipeline ADC for Wideband CDMA Applications

This paper presents a 7-bit 64 MS/s pipeline A/D convertersuitable for wideband CDMA applications. Targeting atachieving low power dissipation at high speed, techniques suchas digital correction and optimal scaling of capacitor valuehave been employed. Switched-Opamp technique is used tofurther reduce power consumption. This ADC is implemented in0.5 m standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.     

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHzfor ADSL applications

The design of a high-resolution, high-speed, delta-sigma analog to-digital converter that operates from a single 3.3-V supply is presented. This supply voltage presents several design problems, such as reduced signal swing and nonzero switch resistance in the switched-capacitor circuits. These problems are tackled in this design by a careful optimization at the system level and by a detailed analysis of several circuit nonidealities. The converter uses a 2-1-1 cascade topology with optimized coefficients. For an oversampling-ratio of only 24, the converter achieves a signal-to-noise ratio of 87 dB, a signal-to-(noise+distortion) ratio of 82 dB, and an input dynamic range of 15 bits after comb filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line applications of 1.1 MHz. It is implemented in a 0.5-μm CMOS technology, in a 5-mm² die area, and consumes 200 mW from a 3.3-V power supply     

A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

This paper presents a second-order ΔΣ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-μm, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits     

CMOS low-distortion high-frequency variable-gain amplifier

The overall system performance of mixed-signal CMOS IC's is largely determined by the dynamic performance of the analog front-ends. System features are, in contrast, mainly set by the digital architecture. In order to optimize the dynamic range of the system and to minimize the sensitivity to substrate noise, the analog-to-digital converter (ADC) has to be preceded by a variable-gain amplifier (VGA) and a differential circuit topology for the complete front-end to be adopted. Since most of present-day applications are based on single-sided signal source definitions, the differential-input VGA must be able to perform a single-to-differential signal conversion. This paper describes the principle and design of a differential CMOS low-distortion variable-gain amplifier for high-frequency (video) applications. Experimental results of the circuit show total harmonic distortion figures better than -60 dB and a gain accuracy of 0.05 dB over the -2 to +12 dB gain range for single-sided input signals     

A low-distortion monolithic wide-band amplifier

A wide-band monolithic amplifier is described which realizes 20-dB gain and 250-MHz bandwidth using an 800-MHz integrated-circuit process. At 0-dBm signal levels, second- and third-order inter-modulation distortion levels are below -55 and -42 dB, respectively, across the band. Terminal impedances are matched to 75 /spl Omega/ with VSWR better than 1.7. Both circuit and process design are described as well as computer optimization of circuit performance.     

A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/spl mu/m CMOS

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.