Estimation of pulsed laser-induced single event transient in a partially depleted silicon-on-insulator 0.18-μm MOSFET

In this paper, we investigate the single event transient(SET) occurring in partially depleted silicon-on-insulator(PDSOI) metal–oxide–semiconductor(MOS) devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-μm single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and analyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test(DUT). The dependences of SET characteristics on drain-induced barrier lowering(DIBL) and the parasitic bipolar junction transistor(PBJT) are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.     

First-Principles Calculations of Atomic and Electronic Properties of T1 and In on Si（111）

The atomic and electronic structures of T1 and In on Si（111） surfaces are investigated using the firstprinciples total energy calculations. Total energy optimizations show that the energetically favored structure is 1/3 ML T1 adsorbed at the T4 sites on Si（111） surfaces. The adsorption energy difference of one T1 adatom between （√3 × √3） and （1 × 1） is less than that of each In adatom. The DOS indicates that TI 6p and Si 3p electrons play a very important role in the formation of the surface states. It is concluded that the bonding of TI adatoms on Si（111） surfaces is mainly polar covalent, which is weaker than that of In on Si（111）. So T1 atom is more easy to be migrated than In atom in the same external electric field and the structures of T1 on Si（111） is prone to switch between （√3 × √3） and （1 × 1）.     

Development of a multi-channel readout ASIC for a fast neutron spectrometer based on GEM-TPC

A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier （GEM）-Time Projection Chamber （TPC）. Charge Amplifier and Shaping Amplifier for GEM （CASAGEM） integrates 16＋1 channels： 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board （PCB） was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.     

Proposal of the readout electronics for the WCDA in the LHAASO experiment

The LHAASO （Large High Altitude Air Shower Observatory） experiment is proposed for a very high energy gamma ray source survey, in which the WCDA （Water Cherellkov Detector Array） is one of the major coinponents. In the WCDA, a total of 3600 PMTs are placed under water in four ponds, each with a size of 150m×150 m. Precise time and cimrge measurement is required for the PMT signals, over a large signal amplitude range from a single P.E. （photo electron） to 4000 P.E. To fulfill the high requirement of a signal measurement in so many front end nodes scattered in a large area, special techniques are developed, such as multiple gain readout, hybrid transmission of clocks, commands and data, precise clock phase alignment and new trigger electronics. We present the readout electronics architecture for the WCDA and several prototype modules, which are now being testedin the laboratory.     

A prototype silicon detector system for space cosmic-ray charge measurement

A readout electronics system used for space cosmic-ray charge measurement for multi-channel silicon detectors is introduced in this paper, including performance measurements. A 64-channel charge sensitive ASIC (VA140) from the IDEAS company is used. With its features of low power consumption, low noise, large dynamic range, and high integration, it can be used in future particle detecting experiments based on silicon detectors.     

Study of a multi-wire proportional chamber with a cathode strip and delay-line readout

The design principle for a multi-wire proportional chamber with a cathode strip and delay-line readout is described. A prototype chamber of a size of 10 cm×10 cm was made together with the readout electronics circuit. A very clean signal with very low background noise was obtained by applying a transformer between the delay-line and the pre-amplifier in order to match the resistance. Along the anode wire direction a position resolution of less than 0.5 mm was achieved with a ^55Fe-5.9 keV X ray source. The simple structure, large effective area and high position resolution allow the application of a gas chamber of this kind to many purposes.     

An X-ray imaging device based on a GEM detector with delay-line readout

An X-ray imaging device based on a triple-GEM （Gas Electron Multiplier） detector, a fast delay-line circuit with 700 MHz cut-off frequency and two dimensional readout strips with 150 μm width on the top and 250 μm width on the bottom, is designed and tested. The localization information is derived from the propagation time of the induced signals on the readout strips. This device has a good spatial resolution of 150 μm and works stably at an intensity of 105 Hz/mm2 with 8 keV X-rays.     

Breakdown characteristics of AIGaN/GaN Schottky barrier diodes fabricated on a silicon substrate

In this work, the breakdown characteristics of AlGaN/GaN planar Schottky barrier diodes （SBDs） fabricated on the silicon substrate are investigated. The breakdown voltage （BV） of the SBDs first increases as a function of the anodeto-cathode distance and then tends to saturate at larger inter-electrode spacing. The saturation behavior of the BV is likely caused by the vertical breakdown through the intrinsic GaN buffer layer on silicon, which is supported by the post-breakdown primary leakage path analysis with the emission microscopy. Surface passivation and field plate termination are found effective to suppress the leakage current and enhance the BV of the SBDs. A high BV of 601 V is obtained with a low on-resistance of 3.15 mΩ·cm^2.     

Forward and reverse electron transport properties across a CdS/Si multi-interface nanoheterojunction

The electron transport behavior across the interface plays an important role in determining the performance of op- toelectronic devices based on heterojunctions. Here through growing CdS thin film on silicon nanoporous pillar array, an untraditional, nonplanar, and multi-interface CdS/Si nanoheterojunction is prepared. The current density versus voltage curve is measured and an obvious rectification effect is observed. Based on the fitting results and model analyses on the forward and reverse conduction characteristics, the electron transport mechanism under low forward bias, high forward bias, and reverse bias are attributed to the Ohmic regime, space-charge-limited current regime, and modified Poole-Frenkel regime respectively. The forward and reverse electrical behaviors are found to be highly related to the distribution of inter- facial trap states and the existence of localized electric field respectively. These results might be helpful for optimizing the preparing procedures to realize high-performance silicon-based CdS optoelectronic devices.     

High-efficiency focusing grating coupler with optimized ultra-short taper

A novel high-efficiency focusing non-uniform grating coupler is proposed to couple light into or off silicon photonic chips for large-scale silicon photonic integration. This kind of grating coupler decreases the transition length of the linking taper between the grating and the single-mode waveguide by at least 80%. The radian of the grating lines and the size of the taper are optimized to improve the coupling efficiency. An experimental coupling efficiency of ~ 68% at 1556.24 nm is obtained after optimization and the whole size of the grating is 12 μm × 30 μm, with a very short taper transition of ~15 μm long.     

On-chip optical pulse shaper for arbitrary waveform generation

We propose and demonstrate a silicon-on-insulator(SOI) on-chip optical pulse shaper based on four-tap finite impulse response. Due to different width designs in phase region of each tap, the phase differences for all taps are controlled by an external thermal source, resulting in an optical pulse shaper. We further demonstrate optical arbitrary waveform generation based on the optical pulse shaper assisted by an optical frequency comb injection. Four different optical waveforms are generated when setting the central wavelengths at 1533.78 nm and 1547.1 nm and setting the thermal source temperatures at 23℃ and 33℃, respectively. Our scheme has distinct advantages of compactness, capability for integrating with electronics since the integrated silicon waveguide is employed.     

Structural properties of a-SiO_x:H films studied by an improved infrared-transmission analysis method

An improved method of fitting point-by-point is proposed to determine the absorption coefficient from infrared(IR)transmittance. With no necessity of empirical correction factors, the absorption coefficient can be accurately determined for the films with thin thicknesses. Based on this method, the structural properties of the hydrogenated amorphous silicon oxide materials(a-SiOx:H) are investigated. The oxygen-concentration-dependent variation of the Si–O–Si and the Si–H related modes in a-SiOx:H materials is discussed in detail.     

Fabrication of pillar-array superhydrophobic silicon surface and thermodynamic analysis on the wetting state transition

Textured silicon （Si） substrates decorated with regular microscale square pillar arrays of nearly the same side length, height, but different intervals are fabricated by inductively coupled plasma, and then silanized by self-assembly octadecyl- trichlorosilane （OTS） film. The systematic water contact angle （CA） measurements and micro/nanoscale hierarchical rough structure models are used to analyze the wetting behaviors of original and silanized textured Si substrates each as a function of pillar interval-to-width ratio. On the original textured Si substrate with hydrophilic pillars, the water droplet possesses a larger apparent CAs （〉 90~） and contact angle hysteresis （CAH）, induced by the hierarchical roughness of microscale pil- lar arrays and nanoscale pit-like roughness. However, the silanized textured substrate shows superhydrophobicity induced by the low free energy OTS overcoat and the hierarchical roughness of microscale pillar arrays, and nanoscale island-like roughness. The largest apparent CA on the superhydrophobic surface is 169.8~. In addition, the wetting transition of a gently deposited water droplet is observed on the original textured substrate with pillar interval-to-width ratio increasing. Furthermore, the wetting state transition is analyzed by thermodynamic approach with the consideration of the CAH effect. The results indicate that the wetting state changed from a Cassie state to a pseudo-Wenzel during the transition.     

Large energy-loss straggling of swift heavy ions in ultra-thin active silicon layers

Monte Carlo simulations reveal considerable straggling of energy loss by the same ions with the same energy in fully-depleted silicon-on-insulator (FDSOI) devices with ultra-thin sensitive silicon layers down to 2.5 nm. The absolute straggling of deposited energy decreases with decreasing thickness of the active silicon layer. While the relative straggling increases gradually with decreasing thickness of silicon films and exhibits a sharp rise as the thickness of the silicon film descends below a threshold value of 50 nm, with the dispersion of deposited energy ascending above ±10%. Ion species and energy dependence of the energy-loss straggling are also investigated. For a given beam, the dispersion of deposited energy results in large uncertainty on the actual linear energy transfer (LET) of incident ions, and thus single event effect (SEE) responses, which pose great challenges for traditional error rate prediction methods.     

Photoelectric characteristics of silicon P–N junction with nanopillar texture:Analysis of X-ray photoelectron spectroscopy

Silicon nanopillars are fabricated by inductively coupled plasma(ICP) dry etching with the cesium chloride(CsCl)islands as masks originally from self-assembly. Wafers with nanopillar texture or planar surface are subjected to phosphorus(P) diffusion by liquid dopant source(POCl3) at 870℃ to form P–N junctions with a depth of 300 nm. The X-ray photoelectron spectroscopy(XPS) is used to measure the Si 2p core levels of P–N junction wafer with nanopillar texture and planar surface. With a visible light excitation, the P–N junction produces a new electric potential for photoelectric characteristic, which causes the Si 2p core level to have a energy shift compared with the spectrum without the visible light.The energy shift of the Si 2p core level is-0.27 eV for the planar P–N junction and-0.18 eV for the nanopillar one. The difference in Si 2p energy shift is due to more space lattice defects and chemical bond breaks for nanopillar compared with the planar one.     

Improved interface properties of an Hf02 gate dielectric GaAs MOS device by using SiNx as an interfacial passivation layer

A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance- voltage characteristic, lower leakage current density （0.785 × 10^-6 Alcm^2 at Vfo ＋ 1 V） and lower interface-state density （2.9 × 10^12 eV^-1 ·cm^-2） compared with other samples with N2- or NH3-plasma pretreatment. The influences of post- deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600 ℃ exhibits better electrical properties than that annealed at 500 ℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.     

Hybrid device for acoustic noise reduction and energy harvesting based on a silicon micro-perforated panel structure

A kind of hybrid device for acoustic noise reduction and vibration energy harvesting based on the silicon micro- perforated panel （MPP） resonant structure is investigated in the article. The critical parts of the device include MPP and energy harvesting membranes. They are all fabricated by means of silicon micro-electro-mechanical systems （MEMS） tech- nology. The silicon MPP has dense and accurate micro-holes. This noise reduction structure has the advantages of wide band and higher absorption coefficients. The vibration energy harvesting part is formed by square piezoelectric membranes arranged in rows. ZnO material is used as it has a good compatibility with the fabrication process. The MPP, piezo- electric membranes, and metal bracket are assembled into a hybrid device with multifunctions. The device exhibits good performances of acoustic noise absorption and acoustic-electric conversion. Its maximum open circuit voltage achieves 69.41 mV.     

Study on the pre-chopper in CSNS LEBT

Physical designing of the pre-chopper in CSNS LEBT is carried out, which includes the deflecting voltage, the length and the width of the deflecting plates, and the gap between the deflecting plates. The most outstanding feature of the design is that both the gap and the width vary with the beam envelope size. So both the requried deflecting voltage and the loaded capacitance are lowered. In order to avoid destruction of the space charge neutralization by the pre-chopper in the whole LEBT, an electron-trapping electrode is arranged to confine the electrostatic field of the pre-chopper to the local area. To examine the reliability of the pre-chopping design in CSNS LEBT, a similar pre-chopping design in ADS RFQ LEBT is set up and an experiment on the pre-chopper is prepared. 3-dimensional simulations are carried out to determine the loaded capacitance and the applied voltage of the electron-trapping electrode.     

Matching by solenoids in space charge dominated LEBTs

The betatron matching of a rotationally asymmetric beam in space charge dominated low-energy beam transports （LEBTs） where solenoids are used for the transverse matching has been studied. For better understanding, the coupling elements of a beam matrix are interpreted in special forms that are products of a term defined by the Larmor rotation angle and another by the difference between the beam matrix elements in the two transverse planes. The coupling form originally derived from the rotationally symmetric field in solenoids still holds when taking into account the rotationally asymmetric space charge forces that are due to the unequal emittance in the two transverse planes. It is shown in this paper that when an LEBT mainly comprising solenoids transports a beam having unequal emittance in the two transverse planes and the linear space charge force is taken into account, the initial Twiss parameters can be modified to obtain the minimum and equal emittance at the LEBT exit. The TRACE3D calculations also prove the principle. However, when quadrupoles that are also rotationally asymmetric are involved in between solenoids, the coupling between the two transverse planes becomes more complicated and the emittance increase is usually unavoidable. A matching example using the CSNS （China Spallation Neutron Source） LEBT conditions is also presented.     

AlOx prepared by atomic layer deposition for high efficiency-type crystalline silicon solar cell

The influence of atomic layer deposition parameters on the negative charge density in AlOx film is investigated by the corona-charge measurement. Results show that the charge density can reach up to -1.56×10^12 cm%-2 when the thickness of the film is 2.4 nm. The influence of charge density on cell conversion efficiency is further simulated using solar cell analyzing software （PC1D）. With AlOx passivating the rear surface of the silicon, the cell efficiency of 20.66% can be obtained.