氮化铝基板薄膜金属化技术

氮化铝陶瓷由于具有热导率高等一系列综合优势。在电力电子及功率微电子技术中具有巨大的应用潜力，目前ＡｌＮ基板应用的关键是金属化技术。本文介绍了ＡｌＮ薄膜金属化技术的特点及可靠性测试情况。     

氮化铝基板薄膜金属化工艺研究

氮化铝（ＡＩＮ）基板由于其优良的热性能和无毒性，成为一种重要的微电子材料。本文从以下三方面研究了氮化铝基板的薄膜金属化问题：（１）金属薄膜同ＡＩＮ基板的附着力；（２）ＡＩＮ基板上薄膜电阻的温度系数；（３）ＡＩＮ基板上ＮｉＣｒ薄膜电阻的功率密度。研究结果表明，氮化铝上薄膜金属化层的附着强度可以大于ＡＩＮ陶瓷本身。成功地将薄膜金属化氮化铝基板应用于功率混合电路和功率对晶体管模块中。     

薄膜金属化LTCC基板的薄膜阻碍层对共晶焊的影响

讨论了LTCC工在板薄膜金属化技术中,有效阻碍层的选择对基板共晶焊的影响。实验结果表明,Ti/Ni是一种高可靠性的阻碍层,而且Ti/Ni/Au也是一种较理想的LTCC基板薄膜金属化结构。     

铜溅射聚酰亚胺薄膜

介绍了日本三井东压化学开发的铜溅射聚酰亚胺薄膜的制法、性能、应用。     

薄膜金属化低温共烧陶瓷基板的阻碍层对共晶焊的影响

讨论了低温共烧陶瓷基板薄膜金属化技术中,有效阻碍层的选择对基板共晶焊的剪切强度、互连阻抗、可焊性的影响。试验结果表明,Ti / Ni是一种高可靠性的阻碍层,且Ti / Ni / Au也是一种较理想的低温共烧陶瓷基板薄膜金属化结构。     

陶瓷电路基板的新型金属化技术

研制成功一种新型的陶瓷电路基板的金属化技术，它兼容了薄膜和厚膜技术的优点，采用ＳＥＭ研究了陶瓷基体的浸蚀特性。测量了金属化导体的附着强度、可焊性、薄层电阻、导热能力及微波损耗，并进行了温循和老化等可靠性试验。测试及应用结果表明，采用该技术可在氧化铝瓷基板上制作附着牢固的铜金属化电路图形，其机、电、热性能优良，可靠性好，为微波和混合集成电路衬底金属化技术开辟了新的工艺途径。     

低温共烧陶瓷基板的薄膜金属化

就低温共烧陶瓷(LTCC)基板实用化过程中遇到的问题,研究了LTCC基板的薄膜金属化技术;经复合膜系Ti/Ni/Au薄膜金属化的LTCC基板可满足各项技术指标要求,通过考核证明了用此方法制得的基板可靠性高,完全满足使用要求。     

AlN基板金属化技术的现状

金属化是ＡｌＮ基板走向实用化的关键技术，金属化膜的性能与可靠性直接关系到ＡｌＮ基板走向实用化的关键技术的情况。     

一种新颖的陶瓷基板金属化技术：DBC基板的原理及应用

本文论述了直接敷铜基板的基本原理，技术特点，及以该技术为基础开发的多层ＤＢＣ基板，三维ＤＢＣ基板，水冷ＤＢＣ基板以及ＤＢＣ气密封装产品，介绍了ＤＢＣ基板的应用领域。     

TiN/n-GaAs肖特基势垒特性

本文用俄歇能谱(AES)、电流-电压(I-V)和电容-电压(C-V)电学测量等方法,研究了反应溅射制备的TiN/n-GaAs肖特基势垒特性.经800℃高温热退火后,TiN/n-GaAs势垒具有良好的整流特性和高温稳定性,其势垒高度为0.80cV,理想因子n为1.07.同时还观察到许多有意义的结果:即随着退火温度的升高(从500℃到800℃),TiN/n-GaAs肖特基二极管的势垒高度增大,势垒电容减小和二极管反向击穿电压增大.我们认为这可能与溅射过程中GaAs衬底中掺氮有关,并用Shannon模型(即金属/P-GaAs/n-GaAs结构)解释了以上结果.研究结果表明,在自对准GaAs MESFET工艺中,TiN是一种很有希望的栅材料.     

AlN基片氧化及金属化

研究了 Al N陶瓷高温氧化对金属化结合强度的影响。在 80 0℃、 10 0 0℃、 12 0 0℃和 140 0℃下对 Al N基片进行了高温处理 ,并用 XRD和 SEM分析了氧化结果。从 12 0 0℃开始 ,基片表面有较明显的氧化 ,140 0℃时 ,基片内部氧化明显。在氧化后的 Al N基片上金属化布线 ,发现表面轻微氧化的 Al N基片和金属化强度有一些提高 ,但氧化过度 ,反而会使金属化结合强度大幅度下降。     

Structural and Passivative Behaviors of Cu(In) Thin Film

This investigation prepares a low-resistivity and self-passivated Cu(In) thin film. The dissociation behaviors of dilute Cu-alloy thin films, containing 1.5–5at.%In, were prepared on glass substrates by a cosputter deposition, and were subsequently annealed in the temperature range of 200–600 °C for 10–30 min. Thus, self-passivated Cu thin films in the form In₂O₃/Cu/SiO₂ were obtained by annealing Cu(In) alloy films at an elevated temperature. Structural analysis indicated that only strong copper diffraction peaks were detected from the as-deposited film, and an In₂O₃ phase was formed on the surface of the film by annealing the film at an elevated temperature under oxygen ambient. The formation of In₂O₃/Cu/SiO₂ improved the resistivity, adhesion to SiO₂, and passivative capability of the studied film. A dramatic reduction in the resistivity of the film occurred at 500 °C, and was considered to be associated with preferential indium segregation during annealing, yielding a low resistivity below 2.92 μΩcm. The results of this study can be potentially exploited in the application of thin-film transistor–liquid crystal display gate electrodes and copper metallization in integrated circuits.     

Diffusion barrier performance of W/Ta-W-N double layers for Cu metallization

In this work, the properties of Cu/W/Ta-W-N/Si film stacks were studied. Adding a thin W layer to a stable Ta-W-N diffusion barrier significantly affected the whole metallization system. The introduction of a thin W interlayer caused a significant change of the system while increasing the stability of the film. The tandem barrier was demonstrated to be stable up to 800 °C by the performed analytical barrier tests.     

铜布线工艺中阻挡层钽膜的研究

从钽膜质量的角度研究了用溅射方法在硅衬底上得到的 60 nm钽膜对铜硅互扩散的阻挡效果 ,钽膜的质量通过对硅衬底的表面处理以及钽膜的淀积速率来控制。研究发现 ,适当的硅衬底表面处理对钽膜是否能产生良好的防扩散能力起着关键的作用。本研究还得到了能有效阻挡铜硅接触的钽膜的淀积速率。     

Cu金属化系统双扩散阻挡层的研究

采用二次离子质谱仪(SIMS)测试了SiON和Ta双层扩散阻挡层及Ta扩散阻挡层的阻挡性能;采用X射线衍射仪(XRD)测量了沉积态有Ta阻挡层和无阻挡层Cu膜的晶体学取向结构;利用电子薄膜应力测试仪测量了具有双层阻挡层Cu膜的应力分布状况。测试结果表明,双阻挡层中Ta黏附层有效地将Cu附着于Si基片上,并对Cu具有一定的阻挡效果,而SiON层则有效地阻止了Cu向SiO2中的扩散。与Ta阻挡层相比,双阻挡层具有较好阻挡性能。有Ta阻挡层的Cu膜的{111}织构明显强于无阻挡层的Cu膜。离子注氮后,薄膜样品应力平均值为206MPa;而电镀Cu膜后,样品应力平均值为-661.7MPa。     

钽薄膜淀积速率与阻挡效果的研究

在硅衬底上用不同淀积速率溅射得到了 60 nm厚钽薄膜作为铜布线工艺中的扩散阻挡层。样品在退火前后 ,用二次离子质谱仪 (SIMS)对钽膜的阻挡效果进行鉴定 ,原子力显微镜 (AFM)分析了钽薄膜的形貌结构。研究发现不同淀积速率制作的钽膜由于其结构的差异对铜硅互扩散有着不同的阻挡效果 ,并提出样品在退火时 ,薄膜晶粒的重结晶过程是导致阻挡层失效的重要因素之一     

Interfacial Reactions Between Pb-Free Solders and In/Ni/Cu Multilayer Substrates

This study investigates the interfacial reactions between Sn-3.0wt.% Ag-0.5wt.%Cu (SAC) and Sn-0.7wt.%Cu (SC) on In/Ni/Cu multilayer substrates using the solid–liquid interdiffusion bonding technique. Samples were reflowed first at 160°C, 180°C, and 200°C for various periods, and then aged at 100°C for 100 h to 500 h. The scalloped Cu₆Sn₅ phase was formed at the SAC/In/Ni/Cu and SC/In/Ni/Cu interfaces. When the reflowing temperatures were 160°C and 180°C, a ternary Ni-In-Sn intermetallic compound (IMC) was formed when the samples were further aged at 100°C. This ternary Ni-In-Sn IMC could be the binary Ni₃Sn₄ phase with extensive Cu and In solubilities, or the ternary Sn-In-Ni compound with Cu solubility, or even a quaternary compound. As the reflow temperature was increased to 200°C, only one Cu₆Sn₅ phase was formed at the solder/substrate interface with the heat treatment at 100°C for 500 h. Mechanical test results indicated that the formation of the Ni-In-Sn ternary IMC weakened the mechanical strength of the solder joints. Furthermore, the solid–liquid interdiffusion (SLID) technique in this work effectively reduced the reflow temperature.     

Si基CdTe复合衬底分子束外延研究

文章引入晶格过渡的Si/ZnTe /CdTe作为复合外延基底材料,以阻挡Si/HgCdTe之间大晶格失配产生的高密度位错。通过对低温表面清洁化、面极性控制和孪晶抑制等的研究,解决了Si基CdTe分子束外延生长中诸多的技术难题。在国内首次采用分子束外延(MBE)的方法获得了大面积的Si基CdTe复合衬底材料,对应厚度为4～4. 4μm Si/CdTe (211)样品双晶半峰宽的统计平均结果为83弧秒,与相同厚度的GaAs/CdTe (211)双晶平均水平相当。     

Diffusion Barrier Behaviors of V-Ta,V-Ta-N and V-Ta/V-Ta-N Alloy Films in Cu Interconnects

The V-Ta, V-Ta-N and V-Ta/V-Ta-N alloy barrier layers with thickness of 50 nm were deposited on Si (100) substrates by magnetron sputtering and then the 300 nm thick Cu films were prepared on the barrier layers to obtain Cu/V-Ta/Si, Cu/V-Ta-N/Si and Cu/V-Ta/V-Ta-N/Si multilayer films. The multilayer film samples were subsequently annealed at 300°C–750°C temperatures for 1 h in vacuum atmosphere. The crystal structure, surface morphology and sheet resistance were characterized by grazing incidence x-ray diffraction (GXRD), electron probe microanalysis (EPMA), scanning electron microscopy (SEM) and four-point probe (FPP) analysis to investigate the diffusion barrier behavior of the V-Ta, V-Ta-N and V-Ta/V-Ta-N alloy barrier layers. The results show that the V-Ta, V-Ta-N and V-Ta/V-Ta-N barrier layers effectively blocked the diffusion of Cu into the Si substrate. When annealed at 700°C, the Cu/V-Ta/Si and Cu/V-Ta/V-Ta-N/Si thin film samples maintained good thermal stability and demonstrated low sheet resistance (～?0.3 Ω cm). Therefore, both the V-Ta and V-Ta/V-Ta-N thin films are promising candidates for use as diffusion barrier layers.