Nonlinear source and drain resistance in recessed-gateheterostructure field-effect transistors

We have profiled the parasitic source and drain resistances versus current in recessed-gate HFET's with heavily-doped caps, using an InAlAs/n⁺-InP HFET as a vehicle. We observe a dramatic reduction in the parasitic resistances at moderate-to-high currents as significant current passes through the cap. Consequently, we note very little dependence in g, on the length of the extrinsic gate-source region. This is an experimental verification of predictions of two-layer models in the literature     

A five-parameter model for current and cross modulation in field-effect transistors with high drain voltage

A new five-parameter model for the behavior of field-effect transistors with high drain voltage has been developed. The resulting single expression is shown to predict the drain-current-gate-voltage characteristics of a variety of devices with an accuracy of ±0.002 V over many decades of drain current. Several methods for the evaluation of model parameters are discussed. The effect of temperature is successfully included in the model in one case. Cross-modulation characteristics can be calculated which are in qualitative agreement with measurements.     

Subthreshold drain leakage currents in MOS field-effect transistors

There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi, the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Viand Vtxthe surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx. The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.     

Differential drain resistance of field-effect transistors beyond pinch-off: A comparison between theory and experiment

The theoretical computation of the drain characteristics of junction field-effect transistors reported by Kim and Yang has been compared with the experimental measurements in terms of the differential drain resistance. Good agreement between the theory and experiment has been found.     

Modeling current transport in ultra-scaled field-effect transistors

An overview of models used for the simulation of current transport in nanoelectronic devices within the framework of TCAD applications is presented. Modern enhancements of semiclassical transport models based on microscopic theories as well as quantum-mechanical methods used to describe coherent and dissipative quantum transport are specifically addressed. This comprises the incorporation of quantum corrections and tunneling models up to dedicated quantum-mechanical simulators, and mixed approaches which are capable of accounting for both, quantum interference and scattering. Specific TCAD requirements are discussed from an engineer’s perspective and an outlook on future research directions is given.     

Characterization of developing source/drain current of carbon nanotube field-effect transistors with n-doping by polyethylene imine

An unsteady source/drain current induced by the source/drain bias of the n-type carbon nanotube field-effect transistors (n-CNTFETs), based on networked SWNTs, is reported. This current might affect the usual source/drain current regulated by the specified gate voltage and even overweighs the devices’ n-type characteristics. Through doping with polyethylene imine (PEI), the n-type devices here are made from the p-CNTFETs that were fabricated by printing interconnected CNTs between electrodes using the newly proposed laser transfer printing technique. To properly preserve the n-characteristics, devices with the PEI thickness less than 40 nm and with operating source/drain voltage below 0.5 V are recommended.     

Noise associated with substrate current in fine-line NMOS field-effect transistors

The noise manifested by impact-ionization-generated substrate current in fine-line NMOS transistors is studied. It is found that this noise can be considerably above the shot noise level for high drain voltages. The magnitude of this noise is interpreted in terms of an avalanche gain produced by a multistep impact-ionization process involving both holes and electrons. The device structure imposes one positive and one negative feedback loop and exhibits a peak in the noise as a function of the drain voltage.     

Parasitic source and drain resistance in high-electron-mobility transistors

The parasitic source and drain resistances of a high-electron-mobility transistor were analyzed in terms of a two layer transmission line model. The analysis showed that a highly conductive cap layer can function as an extension of the alloyed contact provided that tunneling between the cap layer and the channel is significant. The tunneling between the cap layer and the channel was analyzed in terms of a thermionic-field emission model in which a one dimensional time-dependent WKB transmission probability for the barrier was considered as well as Maxwell-Boltzman statistics for the tunneling carrier distribution. The GaAs cap, GaAlAs layer and 2-DEG channel can then be treated as a distributed resistance element with a characteristic coupling length. A reduction of the parasitic resistance can be obtained for a device structure with a short characteristic coupling length even if there exists an ideal alloyed contact to the 2-DEG channel. A multilayer cap consisting of an undoped GaAs layer inserted between the n-type GaAs and n-type GaAlAs is also proposed to reduce the barrier height for tunneling between the cap layer and the channel. The multilayer cap structure is predicted to appreciably reduce the parasitic resistance at room temperature and still be effective at 77 K.     

Carrier accumulation and space-charge-limited current flow in field-effect transistors

This paper reports an investigation of devices fabricated by lateral diffusion techniques which have non-uniform doping profiles along the channel. The application of a two-dimensional numerical method to a device model representing these devices shows carrier accumulation in the conductive channel. The increase of carrier concentration with the increasing drain-to-source voltages is caused by the interaction of the source and the drain N⁺-regions. This indicates the possibility of the space-charge-limited current which is a different conduction mechanism from that of the conventional devices. From the study of one-dimensional N⁺-N-N⁺ structures, the length-to-L_DE (extrinsic Debye length) ratio of the channel and the crossover voltage have been recognized as important parameters in realizing the space-charge-limited current. The drain characteristics of a device model with a small crossover voltage and a small length-to-L_DE ratio are obtained by a simple analysis. Triode-like characteristics are found for this model as expected.     

A small-signal analytical theory for GaAs field-effect transistors at large drain voltages

Small-signal microwave performance of GaAs field-effect transistors (FET's) at large drain voltages is investigated, using a new analytical model which takes into account the carrier drift-velocity reduction and saturation due to electron upper valley scattering, and the extension of the depletion layer towards a drain side. Both of these play important roles in FET operation at large drain voltages. Small-signal y-parameters are calculated and the transit time effect which occurs in high-frequency operations is shown explicitly. Equivalent FET circuit elements are derived from the obtained y-parameters. Their dependence on device physical parameters, as well as on dc bias conditions, is calculated. The theoretical results are compared with the measured small-signal characteristics of a practical power GaAs FET and a reasonable agreement between them is obtained.     

Flexible air-stable three-dimensional polymer field-effect transistors with high output current density

Flexible air-stable short-channel polymer organic field-effect transistor (OFET) arrays with high saturated output current density are demonstrated by utilizing a novel solution-processed naphthobisthiadiazole (NTz) based donor–acceptor semiconducting polymer (PNTz4T) and designing a three-dimensional vertical channel structure with an extremely large ratio of channel width to channel length. The saturated mean field-effect mobility of 0.16 cm²/V s of the short-channel polymer devices remains over one month resulting in air-stable OFET arrays with high on/off ratio over 10⁶ and powerful current–density exceeding 0.3 A/cm² under low operation voltage, both of which meet the requirements for such applications as driving organic light-emitting diodes in active-matrix displays.     

Effect of induced gate noise at zero drain bias in field-effect transistors

According to classical theories, a MOS transistor with zero source-to-drain voltage behaves like a passive resistor exhibiting channel thermal noise and the effect of induced gate noise vanishes. Here, we show that the effect of induced gate noise persists as conductance fluctuations even under these "equilibrium" conditions without disturbing the Nyquist relationship governing the channel thermal noise.     

Theory of negative resistance of junction field-effect transistors

A general theory of the voltage-controlled negative resistance in a field-effect transistor is presented. The prerequisite to the negative resistance is mathematically determined as a relation among the source-gate voltage, the source-drain voltage, and the pinchoff voltage. It is suggested that there will be a variety of circuit configurations with the positive feedback function applied to the gate of the field-effect transistor. Three basic examples of the practical application of the theory are also given.     

Tunable contact resistance in double-gate organic field-effect transistors

A study of the contact resistance (R_sd) in pentacene-based double-gate transistors is presented. In top-contact transistors, as the negative bias of the additional top-gate bias is increased, R_sd decreases by over five orders of magnitude for small bottom-gate voltages. In bottom-contact transistors, R_sd is reduced by about ten times for all bias values, implying improved charge transport in all operating regimes. The different tunability of R_sd in top/bottom-contact transistors is attributed to different charge injection modulation by the coplanar/staggered top gate. Therefore, double-gate architecture offers a novel and effective approach to limit R_sd and its relevant impacts on organic transistor.     

Gate current in self-aligned n-channel and p-channel pseudomorphicheterostructure field-effect transistors

A report is presented on the results of the study of the gate leakage current in n-channel and p-channel self-aligned pseudomorphic HIGFETs. The authors demonstrate that in these devices the gate leakage current is practically independent of the gate length. This means that the gate current primarily flows into the source and drain contacts through small sections of the channel near the contacts. At large gate voltages, the gate current is limited by the band discontinuities at the heterointerface, similar to the gate current in non-self-aligned heterostructure field-effect transistors     

Unified charge control model and subthreshold current inheterostructure field-effect transistors

A unified analytical charge control model covering the entire range of gate voltages from below and above threshold is developed for heterojunction field-effect transistors (HFETs). This model is based on a new interpretation of the quantized energy levels for the two-dimensional electron gas. It reduces to a classical charge sheet model in the limit of low surface field. The model is used to interpret the experimental data for the subthreshold regime of HFETs. The results indicate wide range variation of the effective acceptor concentration after device fabrication processing in the unintentionally doped GaAs buffer layer     

Ga0.47In0.53As field-effect transistors with a lattice-mismatched reduced leakage current GaAs gate

A lattice-mismatched GaAs gate Ga0.47In0.47As field-effect transistor (LMG-FET) with significantly reduced reverse gate leakage current is reported. The mechanism responsible for this reduction by over two orders of magnitude over previous work has been identified; it is attributed to the confinement of misfit dislocations originating at the GaAs/InGaAs interface. The LMG-FET had a gate leakage current of 0.48 ?A at ? V, and an extrinsic DC transconductance of 104 mS/ mm for a 1.4 ?m gate length and 240 ?m gate width. Further refinements in crystal growth should lead to even lower values of leakage current, making this technology attractive for high-speed logic, as well as lightwave optoelectronic integration.     

Gate leakage current in GaN-based mesa- and planar-type heterostructure field-effect transistors

The excessive gate leakage current of the planar- and mesa-type InAlN/GaN heterostructure field-effect transistors (HFETs) is evaluated. It is found that the gate current of the mesa-type HFETs is higher than that of the planar devices, particularly at low biases. Analyses of the gate current considering different transport mechanisms yielded identical thermionic currents (i.e., an identical Schottky barrier height) but a significantly higher leakage component in the mesa-type HFETs than in the planar devices. This additional current component observed in the mesa-type devices shows a nearly ohmic behavior. Mapping by the electron-beam induced current technique confirms an enhanced current located under the expanded gate contact and on the part of the mesa-sidewall, where the gate contact is placed. Two-dimensional simulation of the device structure shows that considerable part of the gate leakage current flows through the GaN buffer layer. These results underline the importance of a proper design of the device structure and layout (i.e., the use of planar structure with device insulation prepared by ion implantation rather than by mesa technique), and of the preparation of the GaN buffer (it should be semi-insulating) in order to fabricate reliable, low leakage current GaN-based HFETs.     

An analysis of current saturation mechanism of junction field-effect transistors

A two-dimensional numerical analysis has been amde for junction field-effect transistors with small and large values of length-to-width ratio. Comparison of the results for different drain bias voltages shows the cause of the saturation of the drain current and the finite differential drain conductance in the saturation region. The effects of the geometry of the device and the field dependent mobility to the drain characteristics are clarified. Detailed pictures of the free carrier density distribution are presented, and the minimum channel width and the channel length are given for various bias conditions. A conduction path from the source to the drain with appreciable free carrier density has been found for bias conditions normally considered as pinched-off conditions. The drain characteristic with gate bias voltage is seen to be equivalent to that of a device with correspondingly smaller width and zero gate bias.     

Influence of impact ionization on the drain conductance inInAs-AlSb quantum well heterostructure field-effect transistors

Using an InAs-AlSb heterostructure field-effect transistor (HFT) structure modified to incorporate an epitaxial p-type GaSb back gate, we measure the impact ionization current caused by hot electrons in the InAs channel. We show that the impact ionization current is only a small fraction of the deleterious increase in the drain current commonly observed in InAs-based transistors. Most of the drain current rise is caused by a feedback mechanism in which holes escaping into the substrate act like a positively charged parasitic back gate leading to an increase in the electron current flow in the channel by an amount that is large compared to the impact ionization current itself. Removal of the impact-generated holes by the epitaxial back gate breaks the feedback loop, and dramatically improves the DC characteristics of the devices, and increases the range of usable drain voltages