Impact of the CMP process on the electrical properties of ultra low k porous SiOCH

The impact of chemical mechanical polishing (CMP) on SiOCH films (thickness = 300 nm) for the 32-45 nm node Cu-interconnect process is investigated by low-frequency dielectric spectroscopy and thermally stimulated depolarization current (TSDC). After CMP process, the dielectric permittivity is degraded of about 25% in the whole range of the investigated frequency (10⁻¹ Hz-100 kHz). In a same way, the dielectric losses tan δ increase at the lowest frequencies. An annealing (300 °C during 20 min) carried out after CMP induces a reduction of the dielectric permittivity without however reaching the value of initial as-deposited material. In agreement with other published papers focusing on the damage caused by the CMP, OH bonding and water adsorption due to surfactants explain the degradation of these dielectric properties. The identification of OH bonds and an increase in the intensity of CH_x in the 2800-3050 cm⁻¹ range after CMP seems to confirm this point. The moderate temperature of annealing, used to restore layers and to avoid the degradation of copper lines, suppresses the physisorbed water but not the chemisorbed water. TSDC measurements confirm that dipolar relaxation, due to water in the material, result in a peak of relaxation at a temperature around 175 °C.     

Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.     

Diffusion barrier performance of W/Ta-W-N double layers for Cu metallization

In this work, the properties of Cu/W/Ta-W-N/Si film stacks were studied. Adding a thin W layer to a stable Ta-W-N diffusion barrier significantly affected the whole metallization system. The introduction of a thin W interlayer caused a significant change of the system while increasing the stability of the film. The tandem barrier was demonstrated to be stable up to 800 °C by the performed analytical barrier tests.     

Porosity and structure evolution of a SiOCH low k material during post-etch cleaning process

In the back end of line (BEOL) interconnections for 65 nm and beyond technology nodes, the integration of porous dielectric materials is now needed to improve signal propagation. In order to develop and optimize etching and cleaning process steps that may degrade the dielectric material, the characterization of ultra-low k porosity becomes mandatory. In this paper, the impact of wet cleaning with diluted HF solution was characterized depending on several plasma treatments. In particular, we focused on pore sealing effects after plasma and its persistency after wet treatments. It was demonstrated that methyl silsesquioxane (MSQ) thin film dissolution in diluted HF is not linear with process time, meaning that the material is not homogeneous. Depending on the plasma treatment, the thin layer created on the top surface is porous and does not protect the material from chemical dissolution. On contrary, some plasma treatment creates a thin layer with a very low permeability (sealed porosity) that acts as a protective coating against dissolution in diluted HF. Moreover, its porosity remains sealed, and pore sealing effect is not impacted by this cleaning process.     

Evaluation of a PECVD advanced barrier (k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier (k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric (k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

Experimental results on the integration of copper and CVD ultra low k material

The integration of ultra low k materials in copper damascene architecture is one of the main issues in finding microelectronic-process-compatible dielectric materials. The aim of this paper is to show the integration conformity with common equipment and process steps using a PECVD (plasma enhanced chemical vapor deposition) CF polymer ultra low k material in a Cu single damascene architecture (Proceedings of the Advanced Metallization Conference, 2002). The intermetal dielectric low k material used in the described structures has 2.1≤k≤2.3 (k depends on deposition process parameters [Microelectron. Eng. 50 (2000) 7–14]) and the copper was deposited by a metal organic chemical vapor deposition process. After chemical mechanical polishing the structures were characterized by scanning electron microscopy and electrical measurements.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

Effect of Cu content on interfacial reactions between Sn(Cu) alloys and Ni/Ti thin-film metallization

The effect of Cu content in Sn(Cu) alloys on the interfacial reaction between Ni thin film and Sn(Cu) alloys has been investigated. We have found that the variation of Cu content has a strong influence on the spalling of the Ni thin film. With small Cu additives in the Sn, spalling was deferred to longer reflowing time. When the Cu content increased to about 1.0 wt.%, a layer of Cu-Sn compound formed on the Ni thin film, and no spalling was observed after 20-min reflowing. The possible mechanism of spalling deferring is proposed. A Cu flux from the solder to the interface compensated the ripening flux of the semispherical compound grains; therefore, spalling was retarded. The driving force of the Cu flux was attributed to the reduction of Cu solubility caused by the presence of Ni at the interface of the Ni thin film. The Cu flux from solder to the interface is calculated to be in the same order with the ripening flux of the Cu₆Sn₅ compound grains, which confirms the proposed mechanism of spalling deferring. For the Sn(Cu) alloys having Cu content over 1.0 wt.%, the Cu-Sn compound layer grew so fast that the surface of the interfacial compound layer was free of Ni. There was no Cu flux to compensate the ripening flux; therefore, the ripening flux dominated, and spalling occurred after a short reflowing time.     

Electroless deposition and electrical resistivity of sub-100 nm Cu films on SAMs: State of the art

Self-assembled organic monolayers (SAMs) of silanes with -SH, -NH₂ and -C₅H₄N functional groups have been shown recently to act as ultra-thin, robust diffusion barriers at the Cu/SiO₂ and Cu/ultra low-k dielectric interfaces. More generally, SAMs with their tunable surface chemistry are essential elements of future all-wet ULSI metallization with Cu deposited by electroless (ELD) over SAM-functionalized dielectrics. Far too small is known however on the electrical properties of thin metal films formed onto SAM/dielectric substrates. In this paper, we give first a brief literature survey of what is known about Cu films deposited by electroless over dielectrics modified by SAMs. Second, we present our observations of electrical resistivity ρ of sub-100 nm ELD Cu films deposited over the surface of amino-silane SAM/SiO₂ activated by Au monodispersed nano-particles and show that this techniques helps to obtain considerably smaller ρ compared to the previously reported data.     

Study of solvent penetration inside a porous low k material by neutron reflectometry - Influence of material surface modifications and of solvent properties

Porous low k materials are used as insulator in integrated circuits interconnection levels. The impact of plasma post-treatments on such material was studied by neutron reflectometry coupled with deuterated solvents penetration. The porosity of the non-modified material determined by the CD₃CD₂OD adsorption isotherm is 28%. The CD₃CD₂OD and D₂O distributions inside the material modified by plasma were determined during their penetration. Whatever the plasma, even in steady state conditions, the modified materials are not completely filled by the solvents. For the sample modified by NH₃/N₂ plasma, whatever the solvent, the equilibrium is instantaneously reached. The CD₃CD₂OD diffused in all the material whereas the D₂O diffuse only in the modified zone due to its higher hydrophilic property compared to that of the zone located underneath. After fluorocarbon-based and oxidizing plasma the material shows a continuous penetration of the CD₃CD₂OD solvent with a saturation obtained after 150 min whereas, the saturation is reached after 100 min with D₂O. Moreover, D₂O penetrates the zone located underneath the modified surface of the sample which should be hydrophobic. This observation highlights a chemical modification of this zone by the plasma treatment.     

The effect of intermetallic compound morphology on Cu diffusion in Sn-Ag and Sn-Pb solder bump on the Ni/Cu Under-bump metallization

The eutectic Sn-Ag solder alloy is one of the candidates for the Pb-free solder, and Sn-Pb solder alloys are still widely used in today’s electronic packages. In this tudy, the interfacial reaction in the eutectic Sn-Ag and Sn-Pb solder joints was investigated with an assembly of a solder/Ni/Cu/Ti/Si₃N₄/Si multilayer structures. In the Sn-3.5Ag solder joints reflowed at 260°C, only the (Ni_1−x,Cu_x)₃Sn₄ intermetallic compound (IMC) formed at the solder/Ni interface. For the Sn-37Pb solder reflowed at 225°C for one to ten cycles, only the (Ni_1−x,Cu_x)₃Sn₄ IMC formed between the solder and the Ni/Cu under-bump metallization (UBM). Nevertheless, the (Cu_1−y,Ni_y)₆Sn₅ IMC was observed in joints reflowed at 245°C after five cycles and at 265°C after three cycles. With the aid of microstructure evolution, quantitative analysis, and elemental distribution between the solder and Ni/Cu UBM, it was revealed that Cu content in the solder near the solder/IMC interface played an important role in the formation of the (Cu_1−y,Ni_y)₆Sn₅ IMC. In addition, the diffusion behavior of Cu in eutectic Sn-Ag and Sn-Pb solders with the Ni/Cu UBM were probed and discussed. The atomic flux of Cu diffused through Ni was evaluated by detailed quantitative analysis in an electron probe microanalyzer (EPMA). During reflow, the atomic flux of Cu was on the order of 10¹⁶−10¹⁷ atoms/cm²sec in both the eutectic Sn-Ag and Sn-Pb systems.     

Study on electrical characteristics and reliability of fluorinated HfO2 for HKMG

The dielectric properties and reliability of fluorinated HfO₂ have been studied. The fluorinated HfO₂ dielectric treated by NF₃ plasma showed improved dielectric characteristics but resulted in interfacial layer (IL) regrowth during the fluorine plasma treatment process, which led to an oxide capacitance reduction and poor electrical characteristics. Through the analysis of chemical composition and electrical characteristics, it has been revealed that the Hf-O bonds in HfO₂ layer were converted to Hf-F bonds by the plasma treatment and then the dissociated oxygen diffused to the IL. In order to suppress the IL regrowth, newly fluorinated HfO₂ has been developed. Reliability of fluorinated HfO₂ dielectric was sharply improved without a decrease in the oxide capacitance at fluorine plasma treatment conditions of low power and temperature.     

Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO₂ dielectric on the performance of underlying SiO_x (x ⩽ 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiO_x IL beneath the GBs and thinner HfO₂ dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiO_x IL.     

基于灰色理论的低压电器仿真性能与评价

作为20世纪末发展起来的一门新兴学科,灰色理论具有较强的适应性,其着重探究的是概率统计、模糊数学所难以解决的"小样本、不确定信息"等问题,可以结合信息覆盖情况,借助于序列生成所得规律,无需建模,因而在多个领域都有广泛应用.本文以灰色理论为基础,就低压电器软件的仿真性能进行了评价和研究.     

Study on the frequency dependence of electrical and dielectric characteristics of Au/SnO2/n-Si (MIS) structures

In this paper, we present a detailed investigation of the electrical and dielectric properties of the Au/SnO₂/n-Si (MIS) structures. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics have been measured in the frequency range of 1 kHz-1 MHz at room temperature. Calculation of the dielectric constant (?′), dielectric loss (?″), loss tangent (tan δ), ac electrical conductivity (σ_ac), ac resistivity (ρ_ac) and the electric modulus are given in the studied frequency ranges. Experimental results show that the values of dielectric parameters are a strong function of frequency. The decrease of ?′ and ?″ with increasing frequency were observed. In addition the increase of σ_ac with increasing frequency is founded. Also, electric modulus formalism has been analyzed to obtain the experimental dielectric data. The interfacial polarization can be more easily occurred at the lower frequency and/or with the number of interface state density between SnO₂/Si interface, consequently, contribute to the improvement of dielectric properties of MIS structure.     

Effect of via etching process and postclean treatment on via electrical performance

The effects of the via etching process as well as the postclean treatment (PCT) on the electrical performance of vias were studied. Stress-migration (SM) tests were carried out to investigate the effect of temperature. Both the thermal and electrical factors were assessed in the wafer-level conventional electromigration (EM) tests. Our results showed that the removal of the TiN antireflection coating (ARC) layer during via etch results in lower initial via resistance, higher resistance to SM, and longer EM lifetime. On the other hand, with additional PCT, the initial via resistance and SM resistance became worse. The C_xF_y residues¹ induced by the PCT step remain at the bottom of the via and degrade the interface properties. However, the EM lifetime seems to be unaffected by these residues. The better EM performance might be related to the removal of the TiO_xN_y layer by the PCT step.     

Effect of Cross-Interaction between Ni and Cu on Growth Kinetics of Intermetallic Compounds in Ni/Sn/Cu Diffusion Couples during Aging

The solid-state, cross-interaction between the Ni layer on the component side and the Cu pad on the printed circuit board (PCB) side in ball grid array (BGA) solder joints was investigated by employing Ni(15 μm)/Sn(65 μm)/Cu ternary diffusion couples. The ternary diffusion couples were prepared by sequentially electroplating Sn and Ni on a Cu foil and were aged isothermally at 150, 180, and 200°C. The growth of the intermetallic compound (IMC) layer on the Ni side was coupled with that on the Cu side by the mass flux across the Sn layer that was caused by the difference in the Ni content between the (Cu_1−x Ni _x )₆Sn₅ layer on the Ni side and the (Cu_1−y Ni _y )₆Sn₅ layer on the Cu side. As the consequence of the coupling, the growth rate of the (Cu_1−x Ni _x )₆ Sn₅ layer on the Ni side was rapidly accelerated by decreasing Sn layer thickness and increasing aging temperature. Owing to the cross-interaction with the top Ni layer, the growth rate of the (Cu_1−y Ni _y )₆Sn₅ layer on the Cu side was accelerated at 150°C and 180°C but was retarded at 200°C, while the growth rate of the Cu₃Sn layer was always retarded. The growth kinetic model proposed in an attempt to interpret the experimental results was able to reproduce qualitatively all of the important experimental observations pertaining to the growth of the IMC layers in the Ni/Sn/Cu diffusion couple.     

Effects of Ni thickness and reflow times on interfacial reactions between Ni/Cu under-bump metallization and eutectic Sn-Pb solder in flip-chip technology

Flip-chip interconnection technology plays a key role in today’s electronics packaging. Understanding the interfacial reactions between the solder and under-bump metallization (UBM) is, thus, essential. In this study, different thicknesses of electroplated Ni were used to evaluate the phase transformation between Ni/Cu under-bump metallurgy and eutectic Sn-Pb solder in the 63Sn-37Pb/Ni/Cu/Ti/Si₃N₄/Si multilayer structure for the flip-chip technology. Interfacial reaction products varied with reflow times. After the first reflow, layered (Ni_1−x,Cu_x)₃Sn₄ was found between solder and Ni. However, there were two interfacial reaction products formed between solders and the UBM after three or more times reflow. The layered (Ni_1−x,Cu_x)₃Sn₄ was next to the Ni/Cu UBM. The islandlike (Cu_1−y,Ni_y)₆Sn₅ intermetallic compound (IMC) could be related to the Ni thickness and reflow times. In addition, the influence of Cu contents on phase transformation during reflow was also studied.     

Effects of Cu and Pd addition on Au bonding wire/Al pad interfacial reactions and bond reliability

Finer pitch wire bonding technology has been needed since chips have more and finer pitch I/Os. However, finer Au wires are more prone to Au-Al bond reliability and wire sweeping problems when molded with epoxy molding compound. One of the solutions for solving these problems is to add special alloying elements to Au bonding wires. In this study, Cu and Pd were added to Au bonding wire as alloying elements. These alloyed Au bonding wires—Au-1 wt.% Cu wire and Au-1 wt.% Pd wire—were bonded on Al pads and then subsequently aged at 175°C and 200°C. Cu and Pd additions to Au bonding wire slowed down interfacial reactions and crack formation due to the formation of a Cu-rich layer and a Pd-rich layer at the interface. Wire pull testing (WPT) after thermal aging showed that Cu and Pd addition enhanced bond reliability, and Cu was more effective for improving bond reliability than Pd. In addition, comparison between the results of observation of interfacial reactions and WPT proved that crack formation was an important factor to evaluate bond reliability.