Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias $V_{\rm D}$ has a strong effect on GIDL current as compared with the gate bias $V_{\rm G}$ at the same drain--gate voltage $V_{\rm DG}$. It is found that the difference between $I_{\rm D}$ in the off-state $I_{\rm D}-V_{\rm G}$ characteristics and the corresponding one in the off-state $I_{\rm D}-V_{\rm D}$ characteristics, which is defined as $I_{\rm DIFF}$, versus $V_{\rm DG}$ shows a peak. The difference between the influences of $V_{\rm D}$ and $V_{\rm G}$ on GIDL current is shown quantitatively by $I_{\rm DIFF}$, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum $I_{\rm DIFF }$($I_{\rm DIFF,MAX})$ varies linearly with $V_{\rm DG}$ in logarithmic coordinates and also $V_{\rm DG}$ at $I_{\rm DIFF,MAX}$ with $V_{\rm F}$ which is the characteristic voltage of $I_{\rm DIFF}$. The relations are studied and some related expressions are given.     

The research on suspended ZnO nanowire field-effect transistor

This paper reports that a novel type of suspended ZnO nanowire field-effect transistors (FETs) were successfully fabricated using a photolithography process, and their electrical properties were characterized by I--V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors (FET). The fabricated suspended nanowire FETs showed a p-channel depletion mode, exhibited high on--off current ratio of ～10⁵. When V_DS=2.5 V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage V_TH was about 0.6 V, the electron mobility was on average 50.17 cm²/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96× 10²Ω cm at V_GS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.     

A novel Si-rich SiN bilayer passivation with thin-barrier AlGaN/GaN HEMTs for high performance millimeter-wave applications

We demonstrate a novel Si-rich SiN bilayer passivation technology for AlGaN/GaN high electron mobility transistors (HEMTs) with thin-barrier to minimize surface leakage current to enhance the breakdown voltage. The bilayer SiN with 20-nm Si-rich SiN and 100-nm Si$_{3}$N$_{4}$ was deposited by plasma-enhanced chemical vapor deposition (PECVD) after removing 20-nm SiO$_{2}$ pre-deposition layer. Compared to traditional Si$_{3}$N$_{4}$ passivation for thin-barrier AlGaN/GaN HEMTs, Si-rich SiN bilayer passivation can suppress the current collapse ratio from 18.54% to 8.40%. However, Si-rich bilayer passivation leads to a severer surface leakage current, so that it has a low breakdown voltage. The 20-nm SiO$_{2}$ pre-deposition layer can protect the surface of HEMTs in fabrication process and decrease Ga-O bonds, resulting in a lower surface leakage current. In contrast to passivating Si-rich SiN directly, devices with the novel Si-rich SiN bilayer passivation increase the breakdown voltage from 29 V to 85 V. Radio frequency (RF) small-signal characteristics show that HEMTs with the novel bilayer SiN passivation leads to $f_{\rm T}/f_{\rm max}$ of 68 GHz/102 GHz. At 30 GHz and $V_{\rm DS} = 20$ V, devices achieve a maximum $P_{\rm out}$ of 5.2 W/mm and a peak power-added efficiency (PAE) of 42.2%. These results indicate that HEMTs with the novel bilayer SiN passivation can have potential applications in the millimeter-wave range.     

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance ($R_{\rm on,sp}$). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field ($E$-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that $R_{\rm on,sp }$ of the modified structure, and breakdown voltage ($V_{\rm BR}$) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit (${\rm FOM}=V^{2}_{\rm BR}/R_{\rm on,sp}$) is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge ($Q_{\rm gd}$) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the $V_{\rm BR}$ of the device without degradation of dynamic performance.     

Theoretica Study on defects associated with lead vacancies in PbWO4 crystals

The defects associated with lead vacancies(VPd)in lead tungstate crystals(PbWO4) are investigated by the relativistic self-consistent discrete variational embedded cluster method.We focus on the density of states and the effect of Vpb on surroundings,the results show that the existence of Vpb can diminish the bandwidth of WOr^2- group,however,it can neither produce O^- and Pb^3 ions nor result in absorptions at 350 and 420nm,The charge balance of VPb may be evenly compensated by the surrounding oxygen ions.     

Effect of F doping on capacitance－voltage characteristics of SiCOH low-k films metal－insulator－semiconductor structure

This paper investigates the capacitance--voltage ($C$--$V$) characteristics of F doping SiCOH low dielectric constant films metal--insulator--semiconductor structure. The F doping SiCOH films are deposited by decamethylcyclopentasiloxane (DMCPS) and trifluromethane (CHF7755, 6855http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057701https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111779F-SiCOH, low-k dielectrics, capacitance--voltage characteristicProject supported by the National Natural Science Foundation of China (Grant No.~10575074).2/4/2009 12:00:00 AMThis paper investigates the capacitance--voltage ($C$--$V$) characteristics of F doping SiCOH low dielectric constant films metal--insulator--semiconductor structure. The F doping SiCOH films are deposited by decamethylcyclopentasiloxane (DMCPS) and trifluromethane (CHF$_{3})$ electron cyclotron resonance plasmas. With the CHF$_{3}$/DMCPS flow rate ratio from 0 to 0.52, the positive excursion of $C$--$V$ curves and the increase of flat-band voltage $V_{\rm FB}$ from $-6.1$~V to 32.2~V are obtained. The excursion of $C$--$V$ curves and the shift of $V_{\rm FB}$ are related to the change of defects density and type at the Si/SiCOH interface due to the decrease of Si and O concentrations, and the increase of F concentration. At the CHF$_{3}$/DMCPS flow rate ratio is 0.12, the compensation of F-bonding dangling bond to Si dangling bond leads to a small $V_{\rm FB}$ of 2.0~V.半导体结构;电压特性;电容电压;绝缘体;薄膜;金属;电子回旋共振等离子体;兴奋剂This paper investigates the capacitance-voltage （C-V） characteristics of F doping SiCOH low dielectric constant films metal-insulator-semiconductor structure. The F doping SiCOH films are deposited by decamethylcyclopentasilox-ane [DMCPS） and trifluromethane （CHF3） electron cyclotron resonance plasmas. With the CHF3/DMCPS flow rate ratio from 0 to 0.52, the positive excursion of C-V curves and the increase of fiat-band voltage VFB from -6.1 V to 32.2V are obtained. The excursion of C-V curves and the shift of VFB are related to the change of defects density and type at the Si/SiCOH interface due to the decrease of Si and O concentrations, and the increase of F concentration. At the CHF3/DMCPS flow rate ratio is 0.12, the compensation of F-bonding dangling bond to Si dangling bond leads to a small VFB of 2.0V.     

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p$+$ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p$+$ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance ($R_{\rm on,sp}$). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage ($V_{\rm BR}$) and $R_{\rm on,sp}$ ($V_{\rm BR}^{2}R_{\rm on,sp}$) of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.     

Physical analysis of normally-off ALD Al2O3/GaN MOSFET with different substrates using self-terminating thermal oxidation-assisted wet etching technique

Based on the self-terminating thermal oxidation-assisted wet etching technique, two kinds of enhancement mode Al$_{2}$O$_{3}$/GaN MOSFETs (metal-oxide-semiconductor field-effect transistors) separately with sapphire substrate and Si substrate are prepared. It is found that the performance of sapphire substrate device is better than that of silicon substrate. Comparing these two devices, the maximum drain current of sapphire substrate device (401 mA/mm) is 1.76 times that of silicon substrate device (228 mA/mm), and the field-effect mobility ($\mu_{\rm FEmax}$) of sapphire substrate device (176 cm$^{2}$/V$\cdot$s) is 1.83 times that of silicon substrate device (96 cm$^{2}$/V$\cdot$s). The conductive resistance of silicon substrate device is 21.2 $\Omega {\cdot }$mm, while that of sapphire substrate device is only 15.2 $\Omega {\cdot }$mm, which is 61% that of silicon substrate device. The significant difference in performance between sapphire substrate and Si substrate is related to the differences in interface and border trap near Al$_{2}$O$_{3}$/GaN interface. Experimental studies show that (i) interface/border trap density in the sapphire substrate device is one order of magnitude lower than in the Si substrate device, (ii) Both the border traps in Al$_{2}$O$_{3}$ dielectric near Al$_{2}$O$_{3}$/GaN and the interface traps in Al$_{2}$O$_{3}$/GaN interface have a significantly effect on device channel mobility, and (iii) the properties of gallium nitride materials on different substrates are different due to wet etching. The research results in this work provide a reference for further optimizing the performances of silicon substrate devices.     

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress (NBS) is observed for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs), which can recover in a short time. After comparing with the degradation phenomena under negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias illumination stress (PBIS), degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies ($V_{\mathrm{o}}^{+}$) in addition to the commonly reported doubly charged oxygen vacancies ($V_{\mathrm{o}}^{2+}$). Furthermore, the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of $V_{\mathrm{o}}^{+}$ under positive gate bias. The proposed degradation mechanisms are verified by TCAD simulation.     

Degradation mechanisms of current gain in NPN transistors

An investigation of ionization and displacement damage in silicon NPN bipolar junction transistors (BJTs) is presented. The transistors were irradiated separately with 90-keV electrons, 3-MeV protons and 40-MeV Br ions. Key parameters were measured {\em in-situ} and the change in current gain of the NPN BJTS was obtained at a fixed collector current (I_{\rm c}=1~mA). To characterise the radiation damage of NPN BJTs, the ionizing dose D_{\i} and displacement dose D_{\d} as functions of chip depth in the NPN BJTs were calculated using the SRIM and Geant4 code for protons, electrons and Br ions, respectively. Based on the discussion of the radiation damage equation for current gain, it is clear that the current gain degradation of the NPN BJTs is sensitive to both ionization and displacement damage. The degradation mechanism of the current gain is related to the ratio of D_{\rm d}/(D_{\rm d}+D_{\rm i}) in the sensitive region given by charged particles. The irradiation particles leading to lower D_{\rm d}/(D_{\rm d}+D_{\rm i}) within the same chip depth at a given total dose would mainly produce ionization damage to the NPN BJTs. On the other hand, the charged particles causing larger D_{\rm d}/(D_{\rm d}+D_{\rm i}) at a given total dose would tend to generate displacement damage to the NPN BJTs. The Messenger--Spratt equation could be used to describe the experimental data for the latter case.     

An oxide/silicon core/shell nanowire metal-oxide semiconductor field-effect transistor

This paper studies an oxide/silicon core/shell nanowire MOSFET(OS-CSNM).Through three-dimensional device simulations,we have demonstrated that the OS-CSNM has a lower leakage current and higher I on /I off ratio after introducing the oxide core into a traditional nanowire MOSFET(TNM).The oxide/silicon OS-CSNM structure suppresses threshold voltage roll-off,drain induced barrier lowering and subthreshold swing degradation.Smaller intrinsic device delay is also observed in OS-CSNM in comparison with that of TNM.     

Effect of substrate temperature on the growth and properties of boron-doped microcrystalline silicon films

Highly conductive boron-doped hydrogenated microcrystalline silicon (\mu c-Si:H) films are prepared by very high frequency plasma enhanced chemical vapour deposition (VHF PECVD) at the substrate temperatures $T_{\rm S})$ ranging from 90$^\circ$C to 270$^\circ$C. The effects of $T_{\rm S}$ on the growth and properties of the films are investigated. Results indicate that the growth rate, the electrical (dark conductivity, carrier concentration and Hall mobility) and structural (crystallinity and grain size) properties are all strongly dependent on $T_{\rm S}$. As $T_{\rm S}$ increases, it is observed that 1) the growth rate initially increases and then arrives at a maximum value of 13.3 nm/min at $T_{\rm S}$=210$^\circ$C, 2) the crystalline volume fraction ($X_{\rm c})$ and the grain size increase initially, then reach their maximum values at $T_{\rm S}$=140$^\circ$C, and finally decrease, 3) the dark conductivity ($\sigma _{\rm d})$, carrier concentration and Hall mobility have a similar dependence on $T_{\rm S}$ and arrive at their maximum values at $T_{\rm S}$=190$^\circ$C. In addition, it is also observed that at a lower substrate temperature $T_{\rm S}$, a higher dopant concentration is required in order to obtain a maximum $\sigma _{\rm d}$.     

Studying a kind of portable ultra-bright microfocus x-raysource

This paper studies the properties of a kind of portable ultra-bright microfocus x-ray source with the Monte-Carlo method in detail. The new x-ray source consists of an electron-emission system, an electrostatic focusing system and a metal target. A crystal Lanthanum Hexaboride cathode, a Wehnelt grid and an extracted electrode compose the triode electrode electron-gun system. Two equal radius cylinder electrodes form the focusing system. The key factors determining the focus properties of the electron beam such as the ratio D_w/H, grid bias V_g, and the properties of the extracted electrode are numerically studied. The calculated results reveal that when D_w/H, V_g, the length of the extracted electrode, and the distance between the grid and the extracted electrode equals 5, --0.6~kV, 10~mm, and 8~mm respectively, the electron beam focal spot can be concentrated down to 9~μm in radius and a reasonable focal length about 72.5~mm can be achieved, at the same time, the cathode emission currents can be as high as 30~mA.     

Electrical and deep levels characteristics of ZnO/Si heterostructure by MOCVD deposition

ZnO films have been prepared on p-type Si substrates by metal-organic chemical vapour deposition （MOCVD） at different total gas flow rates. The current versus voltage and temperature （I - V - T） characteristics, the deep-level transient spectroscopy （DLTS） and the photoluminescence （PL） spectra of the samples were measured. DLTS shows two deep-level centres of E1 （Ec-0.13±0.02eV） and E2 （Ec-0.43±0.05eV） in sample 1202a, which has a ZnO/p-Si heterostructure. A deep level at Ec-0.13±0.01 eV was also obtained from the I -T characteristics. It was considered to be the same as E1 obtained from DLTS measurement. The emission related to this deep level center was detected by PL spectra. In addition, the energy location and the relative trap density of E1 was varied when the total gas flow rate was changed.     

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

First principle study of nitrogen vacancy in aluminium nitride

In the framework of density functional theory, using the plane-wave pseudopotential method, the nitrogen vacancy ($V_{\rm N})$ in both wurtzite and zinc-blende AlN is studied by the supercell approach. The atom configuration, density of states, and formation energies of various charge states are calculated. Two defect states are introduced by the defect, which are a doubly occupied single state above the valance band maximum (VBM) and a singly occupied triple state below the conduction band minimum (CBM) for wurtzite AlN and above the CBM for zinc-blende AlN. So $V_{\rm N}$ acts as a deep donor in wurtzite AlN and a shallow donor in zinc-blende AlN. A thermodynamic transition level $E({3 + } \mathord{\left/ {\vphantom {{3 + } + }} \right. \kern-\nulldelimiterspace} + )$ with very low formation energy appears at 0.7 and 0.6eV above the VBM in wurtzite and zinc-blende structure respectively, which may have a wide shift to the low energy side if atoms surrounding the defect are not fully relaxed. Several other transition levels appear in the upper part of the bandgap. The number of these levels decreases with the structure relaxation. However, these levels are unimportant to AlN properties because of their high formation energy.     

Critical radius and dipole polarizability for a confined system

The analytical transfer matrix method (ATMM) is applied to calculating the critical radius $r_{\rm c}$ and the dipole polarizability $\alpha_{\rm d}$ in two confined systems: the hydrogen atom and the Hulth\'{e}n potential. We find that there exists a linear relation between $r_{\rm c}^{1/2}$ and the quantum number $n_{r}$ for a fixed angular quantum number $l$, moreover, the three bounds of $\alpha_{\rm d}$ ($\alpha_{\rm d}^{K}$, $\alpha_{\rm d}^{B}$, $\alpha_{\rm d}^{U}$) satisfy an inequality: $\alpha_{\rm d}^{K}\leq\alpha_{\rm d}^{B}\leq\alpha_{\rm d}^{U}$. A comparison between the ATMM, the exact numerical analysis, and the variational wavefunctions shows that our method works very well in the systems.     

Theoretical investigation of incomplete ionization of dopants in uniform and ion-implanted 4H-SiC MESFETs

The effects of incomplete ionization of nitrogen in 4H-SiC have been investigated. Poisson's equation is numerically analysed by considering the effects of Poole--Frenkel, and the effects of the potential on $N^+_\dd$ (the concentration of ionized donors) and $n$ (the concentration of electrons). The pinch-off voltages of the uniform and the ion-implanted channels of 4H-SiC metal-semiconductor field-effect transistors (MESFETs) and the capacitance of the gate are given at different temperatures. Both the Poole--Frenkel effect and the potential have influence on the pinch-off voltage $V_{\rm p}$ of 4H-SiC MESFETs. Although the $C$-$V$ characteristics of the ion-implanted and the uniform channel of 4H-SiC MESFETs have a clear distinction, the effects of incomplete ionization on the $C$-$V$ characteristics are not significant.