High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.     

5.6GHz CMOS低噪声放大器设计

分析了一种射频COMS共源-共栅低噪声放大器的设计电路,采用TSMC 90nm低功耗工艺实现。仿真结果表明:在5.6GHz工作频率,电压增益约为18.5dB;噪声系数为1.78dB;增益1dB压缩点为-21.72dBm;输入参考三阶交调点为-11.75dBm。在1.2V直流电压下测得的功耗约为25mW。     

ADS下CMOS低噪声放大器的设计优化

运用仿真工具ADS,通过对CMOS共源共栅低噪声放大器的共源级栅宽,源级电感以及栅极电感值的扫描仿真,以Smith阻抗圆图的形式给出了一个直观的LNA设计优化流程,近似实现了最佳噪声源阻抗和输入阻抗的同时匹配.按照该方法设计的基于0.18 μm CMOS工艺,工作在1.58 GHz的低噪声放大器,其噪声系数为1.3 dB,S11为-28.4 dB,功耗为3.42 mW,从而很好地证实了该方法的可行性.     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

蓝牙收发器中的CMOS低噪声放大器的设计与测试

介绍了一种基于 0 35 μmCMOS数字工艺、集成于单片蓝牙收发器中的射频低噪声放大器 .在考虑ESD保护和封装的情况下 ,从噪声优化、阻抗匹配及增益的角度讨论了电路的设计方法 .经测试 ,在 2 0 5GHz的中心频率处 ,S11为 - 6 4dB ,S2 1为 11dB ,3dB带宽约为 30 0MHz,噪声系数为 5 3dB .该结果表明 ,射频电路设计需要全面考虑寄生效应 ,需要合适的封装模型以及合理的工艺     

High‐Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P_1dB, and efficiency at P_1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.     

Low‐Voltage CMOS Current Feedback Operational Amplifier and Its Application

A novel low‐voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail‐to‐rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ±0.75 V with a total standby current of 304 µA. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ±1 mA. An application of the CFOA to realize a new all‐pass filter is given. PSpice simulation results using 0.25 µm CMOS technology parameters for the proposed CFOA and its application are given.     

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

A Low‐Voltage High‐Performance CMOS Feedforward AGC Circuit for Wideband Wireless Receivers

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling‐time constraints. This makes the use of traditional closed‐loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast‐settling response. The AGC has been implemented in a 0.35 μm standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 μs.     

Integrated Rail‐to‐Rail Low‐Voltage Low‐Power Enhanced DC‐Gain Fully Differential Operational Transconductance Amplifier

In this paper, we present an integrated rail‐to‐rail fully differential operational transconductance amplifier (OTA) working at low‐supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand‐by power dissipation (lower than 0.17 mW in the rail‐to‐rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 μm), presents a 37 V/μs slew‐rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.     

Measurement‐Based Propagation Channel Characteristics for Millimeter‐Wave 5G Giga Communication Systems

This paper presents millimeter‐wave (mmWave) propagation characteristics and channel model parameters including path loss, delay, and angular properties based on 28 GHz and 38 GHz field measurement data. We conducted measurement campaigns in both outdoor and indoor at the best potential hotspots. In particular, the model parameters are compared to sub‐6 GHz parameters, and system design issues are considered for mmWave 5G Giga communications. For path loss modeling, we derived parameters for both the close‐in free space model and the alpha–beta–gamma model. For multipath models, we extracted delay and angular dispersion characteristics including clustering results.     

Temperature Performance of Doping‐Free Top‐Gate CNT Field‐Effect Transistors: Potential for Low‐ and High‐Temperature Electronics

High‐performance top‐gate carbon nanotube (CNT) field‐effect transistors (FETs) have been fabricated via a doping‐free fabrication process in which the polarity of the CNT FET is controlled by the injection of carriers from the electrodes, instead of using dopants. The performance of the doping‐free CNT FETs is systemically investigated over a wide temperature range, from very low temperatures of down to 4.3 K up to 573 K, and analyzed using several temperature‐dependent key device parameters including the ON/OFF state current and ratio, carrier mobility, and subthreshold swing. It is demonstrated that for ballistic and quasi‐ballistic CNT FETs, the operation of the CNT FETs is largely independent of the presence of dopant, thus avoiding detrimental effects due to dopant freeze‐out at low temperature and dopant diffusion at high temperature, and making it possible to use doping‐free CNT FETs in both low‐ and high‐temperature electronics. A new method is also proposed for extracting the band‐gap and diameter of a semiconducting CNT from the temperature dependent OFF‐state current and shown to yield results that are consistent with AFM measurements.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.     

Low‐Voltage Tunable Pseudo‐Differential Transconductor with High Linearity

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage‐to‐current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of ?67 dB at 1 MHz for an input of 1 V_pp and a supply voltage of 1.8 V.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

High‐Gain Double‐Bulk Mixer in 65 nm CMOS with 830 pW Power Consumption

A low‐power down‐sampling mixer in a low‐power digital 65 nm CMOS technology is presented. The mixer consumes only 830 µW at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 °1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of ?5.9 dBm is achieved.     

Low‐Voltage,High‐Performance Organic Field‐Effect Transistors with an Ultra‐Thin TiO2 Layer as Gate Insulator

We report on our latest improvements in organic field‐effect transistors (OFETs) using ultra‐thin anodized gate insulators. Anodization of titanium (Ti) is an extremely cheap and simple technique to obtain high‐quality, very thin (～ 7.5 nm), pinhole‐free, and robust gate insulators for OFETs. The anodized insulators have been tested in transistors using pentacene and poly(triarylamine) (PTAA) as active layers. The fabricated devices display low‐threshold, normally “off” OFETs with negligible hysteresis, good carrier mobility, high gate capacitance, and exceptionally low inverse subthreshold slope. Device performance is improved via chemical modification of TiO₂ with an octadecyltrichlorosilane (OTS) self‐assembled monolayer (SAM). As the result of this combination of favorable properties, we have demonstrated OFETs that can be operated with voltages well below 1 V.     

Non‐Lithographic Fabrication of All‐2D α‐MoTe2 Dual Gate Transistors

As one of the emerging new transition‐metal dichalcogenides materials, molybdenum ditelluride (α‐MoTe₂) is attracting much attention due to its optical and electrical properties. This study fabricates all‐2D MoTe₂‐based field effect transistors (FETs) on glass, using thin hexagonal boron nitride and thin graphene in consideration of good dielectric/channel interface and source/drain contacts, respectively. Distinguished from previous works, in this study, all 2D FETs with α‐MoTe₂ nanoflakes are dual‐gated for driving higher current. Moreover, for the present 2D dual gate FET fabrications on glass, all thermal annealing and lithography processes are intentionally exempted for fully non‐lithographic method using only van der Waal's forces. The dual‐gate MoTe₂ FET displays quite a high hole and electron mobility over ≈20 cm² V^?1 s^?1 along with ON/OFF ratio of ≈10⁵ in maximum as an ambipolar FET and also demonstrates high drain current of a few tens‐to‐hundred μA at a low operation voltage. It appears promising enough to drive organic light emitting diode pixels and NOR logic functions on glass.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Binary Power Amplifier with 2‐Bit Sigma‐Delta Modulation Method for EER Transmitter

A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2‐bit sigma‐delta (ΣΔ) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2‐bit digitized envelope signals. The 2‐bit ΣΔ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over‐sampling ratio, this technique is best suited for wireless communication with high data rates.