BiCMOS circuits for high speed current mode D/A converters

A new BiCMOS current cell and a BiCMOS current switch for high speed, self-calibrating, current-steering D/A converters are described. The BiCMOS current cell can be realized in a BiCMOS process or in a conventional CMOS process using a substrate PNP transistor, while the BiCMOS current switch is intended for implementation in a BiCMOS process. The performance of these circuits has been demonstrated in 0.8 μm BiCMOS and 1.2-μm CMOS technologies. A detailed noise analysis of the BiCMOS current cell indicates that noise during the calibration phase limits its relative accuracy to about 150 ppm. This is substantiated by measured results which show a relative matching of about 100-150 ppm, which is the equivalent of about 13 b performance. Measurement results also indicate that the absolute accuracy of the BiCMOS current cell is better than 0.5% over the designed current range, which is better than that of previously reported designs. Test results for the BiCMOS current switch indicate that a 10-90% switching time of 0.9 ns has been achieved. Furthermore, the switching time of the new BiCMOS switch is very insensitive to current level and input waveform compared to conventional CMOS switches. A 4-b D/A converter based on these components has been fabricated, and test results have demonstrated that it is functional. This DAC will be used as the internal DAC of a ΣΔ modulator for over-sampled video and digital radio applications     

High speed BiCMOS current mode differential track-and-hold circuit

A new principle for a high speed BiCMOS differential track-and-hold circuit based on current mode processing is presented, and simulation results are given. The main characteristics are an acquisition time of 5.5 ns for 8 bit precision and a small-signal bandwidth of 1 GHz     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

Analogue buffer memory for high speed rate conversion

A new sampled data technique is introduced, capable of providing real-time spectral compression of large input bandwidths, while requiring a single sampling operation to be performed at the lower output data rate. The proposed configuration, based on a tapped delay line and CMOS integrated multiplexers, exhibits dual properties for spectral expansion; unique features are the capability of accepting data directly at RF format, with power consumption and switching speed requirements independent of the maximum processed data rate. Sampling rates as high as 25 MHz are demonstrated, requiring only 2.5 MHz tap switching frequency to be performed for a time compression factor of 10.     

Analysis of BiCMOS buffer for input voltages with finite rise time

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design     

Very high speed and high capacity packet switching for broadbandISDN

The authors discuss and propose a very-high-speed and high-capacity packet-switching (HPS) architecture for a future broadband ISDN (integrated-services digital network). The HPS network accommodates various communication services, such as voice, high-speed data, high-speed still picture, and video services. The proposed architecture has three significant principles: a high-speed oriented simple network protocol, separation of signaling and network control from data transfer, and hardware switching. These principles provide fast- and high-throughput transmission for data packets and reliable transmission and processing for call-control packets. The HPS protocol structure is addressed, which provides high flexibility for various communications services as well as high-speed capability. A 3-Gb/s capacity and building-block-structured packet-switching system architecture, using bus- and loop-type switch fabric, is also presented     

Bypassing omega network for high speed packet switching

A highly regular switching network consisting of several switching stages for output buffering is proposed. Each switching element performs 3×3 switching and has a tail-spared buffer for each input port. According to the performance evaluation of the proposed switching network based on computer simulation, a packet loss ratio of 10^-8 was obtained for a 1024×1024 switching network consisting of 15 stages with the Bernoulli traffic source when the size of tail-spared buffer is 8 and the input traffic load is 0.9     

A high performance differential input CMOS current buffer

In this paper, a high accuracy CMOS differential input current buffer (CB) is proposed which employs super source followers (SSF) as input stage and regulated cascode (RGC) current mirrors as output stage. High accuracy requires very high output resistance and low input resistance. Small signal analysis is performed and it is shown that the proposed CB circuit has very low input impedances at ports n and p due to SSF transistors and also very high output impedance at output port due to RGC current mirrors. The simulation results show 9.72 Ω input resistances at ports n and p, 454 MΩ output resistance at output port with only 625 μW power consumption under ±0.9 V power supplies. The simulations are performed with HSpice using TSMC 0.18 μm process parameters and it is shown that the simulation results are in very good agreement with the theoretical ones.     

Modeling of simultaneous switching noise in high speed systems

Simultaneous switching noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex: due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition theory. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a test vehicle, verifying the validity of the method. In addition a system has been simulated to compute SSN, showing the application of this method for complex systems     

A new PLL frequency synthesizer with high switching speed

A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10²~10³ times higher than conventional PLL synthesizers, and spurs of less than -60 dB     

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

无光缓存多波长光交换的阻塞性能分析

文章分析了多波长光交换在无光缓存条件下节点的阻塞性能,也分析了不同交换网络规模下多链路共享的阻塞性能,提出了加权偏转交换方式,利用网络的空闲交换容量,疏导业务负荷,以进一步降低阻塞率．     

The SINFET: a new high conductance, high switching speed MOS-gated transistor

A new MOS power semiconductor device with a very low on-resistance and a switching speed comparable to conventional n-channel power MOSFETs is described. The fabrication process is similar to that of an n-channel lateral DMOS transistor but with the conventional high-low `ohmic? drain contact replaced by a Schottky contact. In operation, the Schottky contact injects minority carriers to conductivity-modulate the n- drift region, thereby reducing the on-resistance by a factor of about ten compared with those of conventional n-channel power MOSFETs of comparable size and voltage capability. Furthermore, since only a small number of minority carriers are injected, the device speed is comparable to conventional n-channel power MOSFETs.     

Performance evaluation of high speed TCP over optical burst switching networks

Study of TCP performance over OBS networks has been an important problem of research lately and it was found that due to the congestion control mechanism of TCP and the inherent bursty losses in the Optical Burst Switching (OBS) network, the throughput of TCP connections degrade. On the other hand, High Speed TCP (HSTCP) was proposed as an alternative to the use of TCP in high bandwidth-delay product networks. HSTCP aggressively increases the congestion window used in TCP, when the available bandwidth is high and decreases the window cautiously in response to a congestion event. In this work, we make a thorough simulation study of HSTCP over OBS networks. While the earlier works in the literature used a linear chain of nodes as the network topology for the simulation, we use the popular 14-node NSFNET topology that represents an arbitrary mesh network in our study. We also study the performance of HSTCP over OBS for different bandwidths of access networks. We use two different cases for simulations where in the first HSTCP connections are routed on disjoint paths while in the second they contend for resources in the network links. These cases of simulations along with the mesh topology help us clearly distinguish between the congestion and contention losses in the OBS network and their effect on HSTCP throughput. For completeness of study, we also simulate TCP traffic over OBS networks in all these cases and compare its throughput with that of HSTCP. We observe that irrespective of the access network bandwidth and the burst loss rate in the network, HSTCP outperforms TCP in terms of the throughput and robustness against multiple burst losses up to the expected theoretical burst loss probability of 10⁻³.     

A high speed,precision voltage buffer in a submicron CMOS process

A new buffer architecture was introduced by Comer and Comer (1998, International Journal of Electronics, 84, 345). This buffer uses an active feedback network based on a transconductance amplifier. An implementation of the new buffer was done in a CMOS process. The buffer was intended for the output stage of a 10-bit video digital-to-analogue converter. The circuit was fabricated on the American Microsystems 0.6 μm process. Design specifications called for a gain accuracy of 0.1%, an offset voltage shift of no more than 1mV over a commonmode input range of 50% of supply voltage and a bandwidth of 500MHz. The actual circuit showed a gain error of less than 0.1%, a common-mode offset variation of less than 2mV, and a bandwidth of 450MHz.     

自相似业务流下的星上交换全局优化缓冲分配算法

针对空间信息网络星上交换节点缓冲资源有限,提出一种适用于星上交换的缓冲优化分配算法。采用了Crossbar交换模型,在此基础上建立了虚通道自相似排队模型,通过计算每个虚通道缓冲溢出概率并采用遗传算法来实现缓冲资源全局优化分配。仿真结果表明,与均匀分配算法和贪婪分配算法相比,新算法具有更好的延时性能,在同等分组平均时延、业务流自相似程度为0.6和0.8的情况下,新算法比均匀分配算法可分别节省24.5%和26.4%的缓冲资源,并且分配效率比贪婪分配算法提高约21.9%。     

Analysis of the switching speed of a submicrometer-gate CMOS/SOS inverter

The speed of a short-channel CMOS/SOS inverter circuit can be predicted with the use of a simple analytical model. Transistor switching times and stage charging times are assumed to contribute independently to the total propagation delay. The analysis is shown to represent accurately the behavior of 1.5- and 0.9-µm-gate CMOS/SOS ring oscillators.     

Method of improving switching speed

The saturation characteristic of a switching transistor can be improved by using gold doping, buried layers, or clamp circuits. However, some important factors such as switching speed, loading capability, cost, and reliability may have to be sacrificed. The author describes a new technique to significantly improve not only the saturation characteristic, but also the switching speed by utilizing a two-collector-terminal transistor. The TCT structure and theory are presented. Results of experiments using the TCT and the conventional transistor are compared.     

A high slew-rate unity-gain low-voltage buffer with largeactive/quiescent current ratio

A buffer that can source or sink up to 10 mA with a slew rate of 130 V/μs in a series RC load of 500 Ω and 12 nF is introduced. The buffer has a standby current of 400 μA which is reduced to 50 nA in less than 100 ns in power-down mode. It operates with a 2.7-V supply and is designed for personal communications applications such as Digital Enhanced Cordless Telecommunications (DECT). The adaptive biasing technique employed in this design makes it suitable for other applications like high-speed sample-and-hold or transconductance stages     

Evaluation of gassing materials in switching devices using monochromatic high speed imaging technique

The purpose of this paper is to investigate quantitative information on perspective gassing materials to be used in switching devices. Previous work indicates that gassing materials have a strong effect on current interruption and current limiting in these devices. However, few papers have been published to cover quantitative information on the amount of certain gassing species released, such as hydrogen, when the gassing material is exposed to a running arc. Monochromatic high speed imaging technique was employed in this investigation to characterize hydrogen gassing properties of different materials based on hydrogen arc images and nitrogen arc images, respectively. Hydrogen plasma has a very high thermal conductivity that results in high arc voltages during interruption, which is critical to current limiting. Comparison among perspective gassing materials was made. The mass loss results derived from plasma emission intensities showed good agreement with direct mass loss measurements of gassing materials.