Titanium-Based Getter Solution for Wafer-Level MEMS Vacuum Packaging

Ultrahigh-vacuum conditions can be achieved by employing porous absorbent materials such as Ti, Zr, Ta, and Yt. Commercial getters are primarily Zr-based, since Zr possesses the best adsorption characteristics. Titanium is not considered as a candidate, since adsorption of gases by Ti is significantly reduced due to oxidation and other contamination. In the present work, it is demonstrated that the adsorption property of Ti can be substantially enhanced and benchmarked against other Zr-based commercial getters by employing a sacrificial layer such as Ni over Ti, and also by using other surface engineering techniques. It has been confirmed that, in addition to the activation temperature, the vacuum level during getter activation also plays a pivotal role in influencing the adsorption characteristics of Ti. It has been determined that the getter life could be significantly improved by the reversible adsorption characteristic of H₂ gas, facilitating regeneration cycles.     

圆片级真空封装技术在MEMS陀螺中的应用

为维持MEMS硅微陀螺的真空度,利用两次硅-玻璃阳极键合和真空长期维持技术,实现了MEMS硅微陀螺的圆片级真空气密性封装。制作过程包括:先将硅和玻璃键合,在硅-玻璃衬底上采用DRIE工艺刻蚀出硅振动结构;再利用MEMS圆片级阳极键合工艺在10-5 mbar(1 mbar=100 Pa)真空环境中进行封装;最后利用吸气剂实现圆片的长期真空气密性。经测试,采用这种方式制作出的硅微陀螺键合界面均匀平整无气泡,漏率低于5.0×10-8 atm.cm3/s。对芯片进行陶瓷封装,静态下测试得出品质因数超过12 000,并对样品进行连续一年监测,性能稳定无变化。     

Au-In-based Hermetic Sealing for MEMS Packaging for Down-Hole Application

Hermetic sealing of micro-electro mechanical systems (MEMS) sensors for down-hole application requires high-quality void-free bonds, with metallic hermetic sealing being widely used for this purpose. As most of the MEMS sensors cannot withstand high temperatures, transient liquid phase (TLP) bonding is promising for metallic sealing applications, since the re-melting temperature of the bond is much higher than the bonding temperature. In this paper, major issues involving TLP bonding, including non-uniform diffusion kinetics across the interface and the formation of intermetallic compounds prior to bonding for fast reactive metallic systems like Au-In, have been addressed by using diffusion barriers. The performance of various diffusion barriers that include Ti, Ni, and Pt has been evaluated. Ni has been determined to be a prospective candidate, since it averts diffusion to a certain extent prior to TLP bonding. The mechanical strength and hermeticity of the Au-In joints have also been characterized after aging at 300 °C up to 500 h. No major changes in the thermo-mechanical properties of the AuIn and AuIn₂ phases were observed and, hence, these phases are concluded to be thermally stable at this temperature regime. Improvements in hermeticity were confirmed when subjected to high-temperature thermal aging.     

A Novel Test Strategy for Fine Pitch Wafer-Level Packaged Devices

This paper describes an innovative test strategy comprising a compliant elastomer mesh for testing fine pitch wafer-level package (WLP) devices. The test probe, hardware, and sample preparation processes are detailed. The components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB, via, off-chip interconnect, and elastomer mesh probe have been modeled. A complete system-level model, with off-chip interconnects on the WLP device pads, has been developed. The measurement and model demonstrate that the prototype test socket performs at 5 GHz with an insertion loss of about 3 dB. WLP device with Bed-of-Nail interconnects are characterized. Functional test features of the system are also addressed.     

WLCSP封装技术中的集成无源器件

芯片规模封装技术一直倍受高性能、小形状因素解决方案在各类应用中的关注。芯片规模封装与球栅阵列(BGA)封装之间的区别变得不可分辨,已成为“细间距BGA”的同义词。芯片规模封装成本也是业界关注的焦点之一。芯片规模晶圆级封装是提供小形状、高性能和低成本的最快途径。论述了集成无源器件加工、低成本化的晶圆级芯片规模封装技术。     

MEMS器件封装技术

综述了微电子机械系统(MEMS)封装主流技术,包括芯片级封装、器件级封装和系统及封装技术进行了。重点介绍了圆片级键合、倒装焊等封装技术。并对MEMS封装的技术瓶颈进行了分析。     

Cu/Sn等温凝固技术在MEMS气密封装中的应用

研究了Cu/Sn等温凝固键合技术在MEMS气密性封装中的应用。设计了等温凝固键合多层材料的结构和密封环图形,优化了键合工艺,对影响气密性的因素(如密封环尺寸等)进行了分析。在350°C实现了良好的键合效果,其最大剪切强度达到27.7MPa,漏率~2×10-4Pa·cm3/sHe,完全可以满足美国军方标准(MIL-STD-883E)的要求,验证了Cu/Sn等温凝固键合技术在MEMS气密封装中的适用性。     

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss.      

Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device

In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a “Y-shaped” through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft ${hbox {HFSS}}^{rm TM}$ 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around ${hbox {1.9}} times {hbox {10}} ^{-9}~{hbox {atm cc/s}}$ have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the “Y-shaped” through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint.      

Development of Metallic Hermetic Sealing for MEMS Packaging for Harsh Environment Applications

Hermetic sealing of microelectromechanical system sensors is indispensable to ensure their reliable operation and also to provide protection during fabrication. This work proposes two prospective candidates for hermetic sealing for rugged environment applications, i.e., Al-Ge and Pt-In. Al-Ge was chosen due to its compatibility with complementary metal–oxide–semiconductor technology. Pt-In possesses the highest remelting temperature among all the solder systems, which is desired for high-temperature applications in both the energy and aerospace industries. The various bonding parameters for Al-Ge eutectic bonding and Pt-In transient liquid-phase (TLP) bonding have been optimized, and their influence on the bond quality is reported. Optimization of bonding parameters has been carried out with the objective of ensuring void-free bonds. A new configuration for stacking Al-Ge thin films has been demonstrated to tackle the issue of loss of Ge prior to bonding, since native Ge oxides are soluble in deionized water. The impact of solid-state aging prior to Al-Ge eutectic bonding has been investigated. The method of tailoring the phases in the Pt-In joint is also discussed. The prospects and constraints of eutectic and TLP bonding from the hermeticity perspective are discussed in detail. Furthermore, changes in the microstructure under aging at 300°C up to 500 h and the resulting influence on the mechanical properties are presented. The overall finding of this work is that Al-Ge can achieve better mechanical and hermetic performance for high-temperature applications.     

Foreword Wafer-Level Packaging

The four papers in this special section focus on wafer-level packaging. The selected papers cover the state-of-the-art and future development trends for wafer level chip scale packages (WLCSPs) by the leading institutes and industries operating in this field.     

圆片级封装技术

圆片级封装(Wafer-LevelPackaging,WLP)已成为先进封装技术的重要组成部分,圆片级封装能够为芯片封装带来批量加工的规模经济效益。在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。综述了圆片级封装的技术及其发展趋势。     

MEMS器件真空封装工艺研究

MEMS器件的真空封装是整个工艺过程中的难点,封装的质量决定着整个器件的质量和使用寿命。现有的封装工艺,封装后器件内部真空度不能有效保持,是需要在真空下工作的器件的瓶颈。随着吸气剂的广泛使用,使MEMS器件的真空度保持能力大大提高,但现有的封装工艺设备不能满足吸气剂的激活条件。分析了空气阻尼对MEMS器件品质因数的影响,提出一种将现有的真空共晶设备的改进方法,使之能应用于使用吸气剂的MEMS器件的真空封装工艺。     

A 5-Gbps Test System for Wafer-Level Packaged Devices

This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2–5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a $pm$ 18-ps timing accuracy. The generated signals exhibit low jitter ($sim$35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.      

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

Wafer-Level Packaging of Micromechanical Resonators

An approach to low-cost, wafer-level packaging of microelectromechanical systems (MEMS), e.g., microresonators, is reported. The process does not require wafer-to-wafer bonding and can be applied to a wide range of MEMS devices. A sacrificial polymer-placeholder is first patterned on top of the MEMS component of interest, followed by overcoating with a low dielectric constant polymer overcoat. The sacrificial polymer decomposes at elevated temperature, and the volatile products from the sacrificial material permeate through the overcoat polymer leaving an embedded air-cavity around the MEMS structure. Thus, the device is released from the sacrificial polymeric material, housed in a protective overcoat. The protected MEMS device can then be handled and packaged like an integrated circuit. The electrical characteristics of the microresonators before and after packaging were essentially the same, showing the packaging scheme does not alter the device performance. This approach is applicable to both surface and bulk micromachined devices     

晶圆片级芯片规模封装技术(WLCSP)

本文主要介绍了一种新型的 CSP 高级封装——晶圆片级芯片规模封装技术(WLCSP)及其特点,并简述了 CSP 封装的主要特点及发展前景。     

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure.