SiCGe/SiC 异质结及其光电特性的MEDICI 模拟

在对SiC1-xGex三元合金主要特性的研究基础上，利用器件仿真器MEDICI模拟和分析SiCGe/SiC异质结光电二极管的光电特性。计算表明， SiC1-xGex 在Ge组分为0.3时与3C-SiC晶格失配较小，此时的SiCGe/SiC异质结对可见光和近红外光有较好的光谱响应。当P型SiC1-xGex层杂质浓度为1×1015cm-3、厚度1.6μm、x=0.3时，SiC1-xGex /SiC异质结光电二极管对0.52μm可见光有250mA/W左右的响应度，对0.7μm近红外光也有102mA/W左右的响应度。     

Island-growth of SiCGe films on SiC

SiCGe ternary alloys have been grown on SiC by hot-wall low-pressure chemical vapour deposition. It has been found that the samples cxhibit an island configuration, and the island growth of SiCGe epilayer depends on the processing parameters such as the growth temperature. When the growth temperature is comparatively low, the epilayer has two types of islands： onc is spherical island; another is cascading triangular island. With the increase of the growth temperature, the islands change from spherical to cascading triangular mode. The size and density of the islands depend on the growth duration and GeH4 flow-rate. A longer growth time and a larger GeH4 flow-rate can increase the size and density of the island in thc initial stage of the epitaxy. In our case, The optimal growth for a high density of uniform islands occurred at a growth temperature of 1100℃ for l-minute growth, with 10 SCCM GeH4, resulting in a narrow size distribution （about 30nm diameter） and high density （about 3.5 ×10^10 dots/cm2）. The growth follows Stranski- Krastanov modc （2D to 3D modc）, both of the islands and the 2D growth layer have face-centred cubic structure, and the critical thickness of the 2D growth layer is only 2.5 nm.[第一段]     

SiC based Si/SiC heterojunction and its rectifying characteristics

The Si on SiC heterojunction is still poorly understood, although it has a number of potential applications in electronic and optoelectronic devices, for example, light-activated SiC power switches where Si may play the role of an light absorbing layer. This paper reports on Si films heteroepitaxially grown on the Si face of (0001) n-type 6H-SiC substrates and the use of B₂H_6 as a dopant for p-Si grown at temperatures in a range of 700--950~\du. X-ray diffraction (XRD) analysis and transmission electron microscopy (TEM) tests have demonstrated that the samples prepared at the temperatures ranged from 850~℃ to 900~℃ are characterized as monocrystalline silicon. The rocking XRD curves show a well symmetry with FWHM of 0.4339° Omega. Twin crystals and stacking faults observed in the epitaxial layers might be responsible for widening of the rocking curves. Dependence of the crystal structure and surface topography on growth temperature is discussed based on the experimental results. The energy band structure and rectifying characteristics of the Si/SiC heterojunctions are also preliminarily tested.     

Optically controlled characteristics of a new heterojunction field effect transistor

A new heterojunction field effect transistor has been proposed and studied analytically to investigate its suitability as a high speed optical detector. The characteristics of the device have been studied in the dark as well as in the illuminated conditions. In the new structure the Schottky gate of a typical high electron mobility transistor (HEMT) has been replaced by a junction gate in order to facilitate the absorption of optical radiation. The performance of the new device has been compared with that of the existing HEMT structure for similar application. It is seen that the absorption of optical radiation of suitable wavelength in the larger bandgap material results into conductivity modulation of the channel giving rise to a considerable change in the saturation drain current in illuminated conditions. This enables the device to respond to an intensity modulated optical signal. It has further been observed that due to an increased optical absorption region the modified structure shows a much better optical sensitivity than the existing one.     

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.     

含有本征SiGe层的SiGe异质结双极晶体管集电结耗尽层宽度模型

本文分别建立了含有本征SiGe层的SiGe HBT(异质结双极晶体管)集电结耗尽层各区域的电势、电场分布模型,并在此基础上,建立了集电结耗尽层宽度和延迟时间模型,对该模型进行了模拟仿真,定量地分析了SiGe HBT物理、电学参数对集电结耗尽层宽度和延迟时间的影响,随着基区掺杂浓度和集电结反偏电压的提高,集电结耗尽层延迟时间也随之增大,而随着集电区掺杂浓度的提高和基区Ge组分增加,集电结耗尽层延迟时间随之减小. 关键词： SiGe HBT 集电结耗尽层 延迟时间     

Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit

A novel silicon carbide(SiC)on silicon(Si)heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer(PBL ...     

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor(LTFET) with a symmetric heteromaterial gate is proposed.Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.     

Enhanced charge carrier injection in heterojunction organic field-effect transistor by inserting an MoO3 buffer layer

A top-contact organic field-effect transistor(OFET) is fabricated by adopting a pentacene/1,1’-bis(di-4tolylaminophenyl) cyclohexane(TAPC) heterojunction structure and inserting an MoO3 buffer layer between the TAPC organic semiconductor layer and the source/drain electrode.The performances of the heterojunction OFET,including output current,field-effect mobility,and threshed voltage,are all significantly improved by introducing the MoO3 thin buffer layer.The performance improvement of the modified heterojunction OFET is attributed to a better contact formed at the Au/TAPC interface due to the MoO3 thin buffer layer,thereby leading to a remarkable reduction of the contact resistance at the metal/organic interface.     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.     

SiC/SiC复合材料第一壁热工设计

以日本原子力研究所那珂研究所聚变堆设计室进行的先进稳态托卡马克聚变堆2（A－SSTR2）概念设计为基础，对SiC/SiC复合材料包层／第一壁热工设计进行了分析计算。通过选取各种几何位形和材料敏感特性参数，用有限元法进行了大量的热工计算，以最高温度、最大热应力为基础建立了包层／第一壁设计窗口，选取了满足热工要求的最佳设计方案，对今后的工程设计具有指导作用和重要的参考价值。     

超结硅锗碳异质结双极晶体管机理研究与特性分析优化

提出一种超结硅锗碳异质结双极晶体管(SiGeC HBT)新结构.详细分析了新结构中SiGeC基区和超结结构的引入对器件性能的影响,并对其电流输运机制进行研究.基于SiGeC/Si异质结技术,新结构器件的高频特性优良;同时超结结构的存在,在集电区内部水平方向和垂直方向都建立了电场,二维方向上的电场分布相互作用大大提高了新结构器件的耐压能力.结果表明:超结SiGeC HBT与普通结构SiGeC HBT相比,击穿电压提高了48.8%;更重要的是SiGeC HBT器件中超结结构的引入,不会改变器件高电流增益、高频率特性的优点;新结构器件与相同结构参数的Si双极晶体管相比,电流增益提高了10.7倍,截止频率和最高震荡频率也得到了大幅度改善,很好地实现了高电流增益、高频率特性和高击穿电压三者之间的折中.对超结区域的柱区层数和宽度进行优化设计,随着柱区层数的增多,击穿电压显著增大,电流增益有所提高,截止频率和最高震荡频率减低,但幅度很小.综合考虑认为超结区域采用pnpn四层结构是合理的.     

CuI/Al双层电极的有机场效应晶体管

制备了CuI/Al为源极和漏电极的并五苯基场效应晶体管.相对于纯金属(Al, Au)电极的晶体管,所研制的晶体管的迁移率、阈值电压VT、开关电流比I_on/I_off等参数都有明显改善.研究发现,在Al电极与并五苯半导体之间引入CuI作为空穴注入层,能够明显降低Al电极与并五苯之间的空穴注入势垒.紫外-可见光谱和X射线光电子能谱数据表明,这种空穴注入势垒的降低源自并五苯和Al向CuI的电子转移. 关键词： 有机场效应晶体管 CuI/Al双层源漏电极 电子转移     

Comparison of fibre/matrix interface strength for a 3D woven SiC/SiC composite

The fibre/matrix interface shear strength, τ _P, was determined by analysis of fibre pullout length distributions for a 3D woven SiC/SiC-based composite that had undergone tensile testing between room temperature and 1300°C in vacuum and air. Data was compared with the fibre/matrix interface shear strength, τ _S, obtained previously for this system by analysis of in situ fibre strength distributions. τ _P was found to follow the same general trend as that of τ _S and this was explained in terms of the carbon-rich fibre/matrix interface region. However, τ _P was smaller than τ _S by a factor of 3-4 for all cases, but the reason for this remains unclear although several tentative suggestions have been put forward.     

The stability of SiC coating and SiO2/SiC multilayer on the surface of graphite for HTGRs at normal service condition

The stability of SiC coating in helium with a low concentration of O₂, CO₂, and H₂O is a key factor for their application in improvement of oxidation resistance of graphite for high temperature gas-cooled reactors (HTGRs). Through thermodynamic analysis, it is found that the influence factor controlling the critical temperature of passive oxidation for SiC is partial pressure of active gas in helium; the critical temperature of passive oxidation for SiC increases with the partial pressure of O₂, CO₂, and H₂O, SiC is prone to undergo active oxidation in He–CO₂ and He–H₂O system. SiO₂/SiC multilayer coating can improve the oxidation resistance of graphite at higher temperature than SiC coating does under normal operation condition for HTGRs.     

新型宽温区高热稳定性微波功率SiGe 异质结双极晶体管

宽温区大电流下的热不稳定性严重制约着功率SiGe 异质结双极晶体管 (HBT) 在射频和微波电路中的应用.为改善器件的热不稳定性, 本文利用SILVACO TCAD建立的多指功率SiGe HBT模型, 分析了器件纵向结构中基区Ge组分分布对微波功率SiGe HBT电学特性和热学特性的影响. 研究表明, 对于基区Ge组分为阶梯分布的HBT, 由于Ge组分缓变引入了少子加速电场, 使它与均匀基区Ge组分HBT相比, 具有更高的特征频率f_T, 且电流增益β和f_T随温度变化变弱, 这有利于防止器件在宽温区工作时电学特性的漂移.同时, 器件整体温度有所降低, 但器件各指温度分布均匀性较差.考虑多指HBT各发射极指散热能力存在差异, 在器件纵向结构设计为基区Ge组分阶梯分布的同时, 对其横向版图进行发射极指间距渐变结构设计, 用于改善器件各指温度分布的均匀性, 进而提高HBT的热稳定性.结果表明, 与基区Ge组分为均匀分布的等发射极指间距结构HBT相比, 新器件各指温度分布均匀性明显改善, f_T保持了较高的值, 且β和f_T 随温度变化不敏感, 热不稳定性得到显著改善, 显示了新器件在宽温区大电流下工作的优越性. 关键词： SiGe 异质结双极晶体管 Ge组分分布 发射极指间距渐变技术 热稳定性     

TiN/SiC纳米多层膜的生长结构与力学性能

研究了TiN/SiC纳米多层膜中立方SiC（B1cubic SiC）的形成及其对TiN/SiC多层膜力学性能的影响.结果表明：在TiN/SiC多层膜中，非晶态的SiC层在厚度小于0.6nm时形成立方结构并与TiN形成共格外延生长的超晶格柱状晶，使多层膜产生硬度和弹性模量显著升高的超硬效应，最高硬度超过60GPa.SiC随着层厚的增加转变为非晶相，从而阻止了多层膜的共格外延生长，使薄膜呈现TiN纳米晶和SiC非晶组成的层状结构特征，同时多层膜的硬度和弹性模量下降.TiN/SiC纳米多层膜产生的超硬效应与立方 关键词： 立方碳化硅 TiN/SiC纳米多层膜 外延生长 超硬效应     

Novel attributes of AlGaN/AlN/GaN/SiC HEMTs with the multiple indented channel

In this paper, a high performance AlGaN/AlN/GaN/SiC High Electron Mobility Transistor (HEMT) with the multiple indented channel (MIC-HEMT) is proposed. The main focus of the proposed structure is based on reduction of the space around the gate, stop of the spread of the depletion region around the source–drain, and decrement of the thickness of the channel between the gate and drain. Therefore, the breakdown voltage increases, meanwhile the elimination of the gate depletion layer extension to source/drain decreases the gate–source and gate–drain capacitances. The optimized results reveal that the breakdown voltage and the drain saturation current increase about 178% and 46% compared with a conventional HEMT (C-HEMT), respectively. Therefore, the maximum output power density is improved by factor 4.1 in comparison with conventional one. Also, the cut-off frequency of 25.2 GHz and the maximum oscillation frequency of 92.1 GHz for the MIC-HEMT are obtained compared to 13 GHz and 43 GHz for that of the C-HEMT and the minimum figure noise decreased consequently of reducing the gate–drain and gate–source capacitances by about 42% and 40%, respectively. The proposed MIC-HEMT shows a maximum stable gain (MSG) exceeding 24.1 dB at 3.1 GHz which the greatest gain is yet reported for HEMTs, showing the potential of this device for high power RF applications.     

Study on characteristics of a double-conductible channel organic thin-films transistor with an ultra-thin hole-blocking layer

The properties of top-contact organic thin-film transistors (TC-OTFTs) using ultra-thin 2, 9-dimethyl-4, 7-diphenyl-1, 10-phenanthroline (BCP) as a hole-blocking interlayer have been improved significantly and a BCP interlayer was inserted into the middle of the pentacene active layer. This paper obtains a fire-new transport mode of an OTFT device with double-conductible channels. The accumulation and transfer of the hole carriers are limited by the BCP interlayer in the vertical region of the channel. A huge amount of carriers is located not only at the interface between pentacene and the gate insulator, but also at the two interfaces of pentacene/BCP interlayer and pentacene/gate insulator, respectively. The results suggest that the BCP interlayer may be useful to adjust the hole accumulation and transfer, and can increase the hole mobility and output current of OTFTs. The TC-OTFTs with a BCP interlayer at V_DS=-20~V showed excellent hole mobility μ_FE and threshold voltage V_TH of 0.58~cm²/(V\cdots) and --4.6~V, respectively.     

内嵌CuO薄膜对并五苯薄膜晶体管性能的改善

制备了基于内嵌氧化物铜(CuO)薄膜的并五苯薄膜晶体管器件. 将3 nm CuO薄膜内嵌入到并五苯(pentacene)中, 作为空穴注入层, 降低电极与并五苯之间的空穴注入势垒. 相对于纯并五苯薄膜晶体管器件, 研制的晶体管的迁移率、阈值电压(V_TH)、电流开关比(I_on/I_off) 等参数都有明显改善. X射线光电子能谱数据表明, 这种空穴注入势垒的降低源自并五苯向CuO的电子转移.