Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch

In this paper, we have designed a double-gate MOSFET and compared its performance parameters with the single-gate MOSFET as RF CMOS switch, particularly the double-pole four-throw (DP4T) switch, for the wireless telecommunication systems. A double-gate radio-frequency complementary metal-oxide-semiconductor (DG RF CMOS) switch operating at the frequency of microwave range is investigated. This RF switch is capable to select the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the circuit elements (such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, and switching speed) required for the integrated circuit of the radio frequency sub-system of the DG RF CMOS switch and the role of these basic circuit elements are also discussed. These properties presented in the switches due to the double-gate MOSFET and single-gate MOSFET have been discussed.     

Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET

A two-dimensional analytical model for fully depleted cylindrical/surrounding gate MOSFET is presented. We used the evanescent mode analysis to solve the 2D Poisson's equation and to deduce analytically the surface potential and threshold voltage expressions of this device. Comparison with the other models reveals a good agreement.     

由RTD/MOSFET构成的压控振荡器的设计与实现

提出了一种基于负阻器件共振隧穿二极管(RTD)与MOSFET结合的新型压控振荡器(VCO),并利用了高级设计系统(ADS)软件对该振荡器的可行性进行了电路仿真,利用分立RTD、MOSFET器件实现了此种VCO,实际调频范围在20～26 MHz之间。RTD与三端器件的连接方式不同可呈现不同的调制I-V特性,这种调制特性对基于RTD的振荡电路的频率也会产生影响。通过深入研究这种调制对振荡电路频率产生的影响,得到多种不同于常规方法的电压控制频率方式,其中一些具有很好的线性度。因此该电路的研究对于RTD在高频、高速振荡电路中的进一步应用具有重要意义。     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

This paper presents the design and implementation of a new scalable cell‐based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non‐uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self‐routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0.18 µm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing. Copyright © 2006 John Wiley & Sons, Ltd.     

子波长粒度光信号传输的频域均衡设计和性能分析

针对弹性光网络(EON)的应用,提出了一种基于电域子载波复用的子波长粒度光信号传 输技术,具有高灵活性、细 粒度、高效率等特点。同时,电域数字信号处理技术的使用,支持对不同的子波长粒度信号 进行独立的调 制方式、传输速率等灵活配置。为了适应子波长粒度光信号在EON中的传输要求 ,还提出了一 种基于线性频率啁啾导频信号的信道估计和频域均衡(FDE)的方法,重点研究和分析了基于 导频的FDE和基 于训练序列的时域均衡(TDE)的性能对比,以及不同的FDE算法的性能对比。仿真结 果表明,基于线性频率 啁啾导频信号的迫零FDE算法,不仅能有效进行色散补偿,改善系统传输性能,而 且具有低算法复杂 度的优势。同时,为了满足了子波长粒度EON对频隙和路由配置的灵活性需求, 通过仿真详 细研究子波长粒度光信号的数目、传输距离和调制阶数等对传输性能的影响。仿真结果表 明,基于线性 频率啁啾导频信号的信道估计和FDE的方法,在不同的光网络配置下均具有良好的 适应性,是实现灵 活可调的光收发机和子波长信号动态重构的关键技术之一。