高k介质在新型半导体器件中的应用

当CMOS器件特征尺寸缩小到45 nm以下, SiO₂作为栅介质材料已经无法满足性能和功耗的需要, 用高 k材料替代SiO₂是必然选择. 然而, 由于高 k材料自身存在局限性, 且与器件其他部分的兼容性差, 产生了很多新的问题如界面特性差、 阈值电压增大、 迁移率降低等. 本文简要回顾了高 k栅介质在平面型硅基器件中应用存在的问题以及从材料、 结构和工艺等方面采取的解决措施, 重点介绍了高k材料在新型半导体器件中的应用, 并展望了未来的发展趋势.     

高k栅介质应变Si SOI MOSFET的阈值电压解析模型

在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOI MOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介 关键词： 应变Si k栅')" href="#">高k栅 短沟道效应 漏致势垒降低     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-kappa gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-kappa gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-kappa dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson’s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal–oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.     

Valence band variation in Si (110) nanowire induced by a covered insulator

In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k$\cdot$p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO₂ insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO₂ insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO₂ insulator, the strain of the HfO₂ gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO₂ insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.     

Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.     

CVD-derived Hf-based High-k Gate Dielectrics

Hf-based high-k gate dielectric has been recently highlighted as the most promising high-k dielectrics for the next-generation CMOS devices with high performance due to its excellent thermal stability and relatively high dielectric constant. This article provides a comprehensive view of the state-of-the-art research activities in advanced Hf-based high-k gate dielectrics grown by chemical-vapor-deposition-based method, including metal-organic-chemical-vapor-deposition (MOCVD), atomic-layer-chemical-vapor-deposition (ALCVD), and plasma-enhanced- chemical-vapor-deposition (PECVD), in CMOS device. We begin with a survey of methods developed for generating Hf-based high-k gate dielectrics. After that, most attention has been paid to the detailed discussion of the latest development of novel Hf-based high-k gate dielectrics grown by CVD. Finally, we conclude this review with the perspectives and outlook on the future developments in this area. This article explores the possible influences of research breakthroughs of Hf-based gate dielectrics on the current and future applications for nano-MOSFET devices.     

High temperature characteristics of ZnO-based MOS-FETs with a photochemical vapor deposition SiO2 gate dielectric

The authors report the fabrication of ZnO-based metal-oxide-semiconductor field effect transistors (MOSFETs) with a high quality SiO₂ gate dielectric by photochemical vapor deposition (photo-CVD) on a sapphire substrate. Compared with ZnO-based metal-semiconductor FETs (MESFETs), it was found that the gate leakage current was decreased to more than two orders of magnitude by inserting the photo-CVD SiO₂ gate dielectric between ZnO and gate metal. Besides, it was also found that the fabricated ZnO MOSFETs can achieve normal operation of FET, even operated at 150 °C. This could be attributed to the high quality of photo-CVD SiO₂ layer. With a 2 μm gate length, the saturated I_ds and maximum transconductance (G_m) were 61.1 mA/mm and 10.2 mS/mm for ZnO-based MOSFETs measured at room temperature, while 45.7 mA/mm and 7.67 mS/mm for that measured at 150 °C, respectively.     

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO₂ layer and are then fully covered by a HfO₂ layer. The HfO₂ is a high-k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance–voltage and conductance–voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.     

Microstructural,chemical bonding,stress development and charge storage characteristics of Ge nanocrystals embedded in hafnium oxide

We have grown Ge nanocrystals (NCs) (4.0–9.0 nm in diameter) embedded in high-k HfO₂ matrix for applications in floating gate memory devices. X-ray photoelectron spectroscopy has been used to probe the local chemical bonding of Ge NCs. The analysis of Ge–Ge phonon vibration using Raman spectroscopy has shown the formation of compressively stressed Ge NCs in HfO₂ matrix. Frequency dependent electrical properties of HfO₂/Ge-NCs in HfO₂/HfO₂ sandwich structures have been studied. An anticlockwise hysteresis in the capacitance–voltage characteristics suggests electron injection and trapping in embedded Ge NCs. The role of interface states and deep traps in the devices has been thoroughly examined and has been shown to be negligible on the overall device performance.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

小尺寸MOSFET隧穿电流解析模型

基于表面势解析模型，通过将多子带等效为单子带，建立了耗尽/反型状态下小尺寸MOSFET直接隧穿栅电流解析模型.模拟结果与自洽解及实验结果均符合较好，表明此模型不仅可用于SiO₂、也可用于高介电常数(k)材料作为栅介质以及叠层栅介质结构MOSFET栅极漏电特性的模拟分析，计算时间较自洽解方法大大缩短，适用于MOS器件电路模拟. 关键词： 隧穿电流 MOSFET 量子机理 解析模型     

Metal carbide-induced negative flatband voltage shift in TaCx and HfCx/HfO2 gate stacks

We systematically investigated the role of the top interface for TaC_x and HfC_x/HfO₂ gate stacks on the effective work function (Φ_m,eff) shift by inserting a SiN layer at the gate/HfO₂ top interface or HfO₂/SiO₂ bottom interface. We found that Φ_m,eff of the TaN gate electrode on HfO₂ was larger than that on SiO₂ because of the HfO₂/SiO₂-bottom-interface dipole. On the other hand, we found that Φ_m,eff values of the TaC_x and HfC_x gate electrodes on HfO₂ agree with Φ_m,eff on SiO₂. This is because the potential offset of the opposite direction with respect to the bottom interface dipole appears at the metal carbide/HfO₂ interface. It is thus concluded that the top interface in the metal carbide/HfO₂ gate stacks causes the negative Φ_m,eff shift.     

Effects of packing materials on the sensitivity of RadFET with HfO2 gate dielectric for electron and photon sources

The radiation sensing field effect transistor (RadFET) with SiO₂ gate oxide has been commonly used as a device component or dosimetry system in the radiation applications such as space research, radiotherapy, and high-energy physics experiments. However, alternative gate oxides and more suitable packaging materials are still demanded for these dosimeters. HfO₂ is one of the most attractive gate oxide materials that are currently under investigation by many researchers. In this study, Monte Carlo simulations of the average deposited energy in RadFET dosimetry systems with different package lid materials for point electron and photon sources were performed with the aim of evaluating the effects of package lids on the sensitivity of the RadFET by using HfO₂ as a gate dielectric material. The RadFET geometry was defined in a PENGEOM package and electron–photon transport was simulated by a PENELOPE code. The relatively higher average deposited energies in the sensitive region (HfO₂ layer) for electron energies of 250?keV–20?MeV were obtained from the RadFET with the Al₂O₃ package lid despite of some deviations from the general tendency. For the photon energies of 20–100?keV, the average amount of energy deposited in RadFET with Al₂O₃ package was higher compared with the other capped devices. The average deposited energy in the sensitive region was quite close to each other at 200?keV for both capped and uncapped devices. The difference in the average deposited energy of the RadFET with different package lid materials was not high for photon energies of 200–1200?keV. The increase in the average deposited energy in the HfO₂ layer of the RadFET with Ta package lid was higher compared with the other device configurations above 3?MeV.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

Low-temperature deposition of stoichiometric HfO2 on silicon: Analysis and quantification of the HfO2/Si interface from electrical and XPS measurements

An understanding of the exact structural makeup of dielectric interface is crucial for development of novel gate materials. In this paper a study of the HfO₂/Si interface created by the low-temperature deposition ultrathin stoichiometric HfO₂ on Si substrates by reactive sputtering is presented. Analysis, quantification and calculation of layer thickness of an HfO₂/Hf-Si-O_x/SiO₂ gate stack dielectrics have been performed, using X-ray photoelectron spectroscopy (XPS) depth profile method, angle resolved XPS and interface modeling by XPS data processing software. The results obtained were found to be in good agreement with the high frequency capacitance-voltage (C-V) measurements. The results suggest a development of a complex three layer dielectric stack, including hafnium dioxide layer, a narrow interface of hafnium silicate and broad region of oxygen diffusion into silicon wafer. The diffusion of oxygen was found particularly detrimental to the electrical properties of the stack, as this oxygen concentration gradient leads to the formation of suboxides of silicon with a lower permittivity, κ.     

A study of GaN MOSFETs with atomic-layer-deposited Al2O3 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al₂O₃ gate dielectrics are fabricated. The device, with atomic-layer-deposited Al₂O₃ as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al₂O₃ as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the Al₂O₃ film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm²/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition Al₂O₃ growth and device fabrication.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应