Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

Impacts of Ti on electrical properties of Ge metal–oxide–semiconductor capacitors with ultrathin high-k LaTiON gate dielectric

Ge Metal–Oxide–Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La₂O₃ ratio, a suitable Ti/La₂O₃ ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×10¹¹ eV⁻¹ cm⁻², and relatively low gate-leakage current density of 2.0×10⁻³ A cm⁻² at a gate voltage of 1 V.     

Current instabilities in dynamic random access memory storage capacitor formed with electron beam deposited Y2O3 dielectric

Metal-oxide-semiconductor (MOS) storage capacitors based on electron beam deposited Y₂O₃ extrinsic dielectric on Si show changes in capacitance density depending on the amorphous and crystalline phases. Bias stress cycle-dependent changes in capacitance density occur due to the non-equilibrium nature of defect states at the Y₂O₃/Si interface after O₂ annealing as a result of the emergence of a 4–8 nm thick SiO₂ film at the interface. Leakage currents show instability under repeated dc bias stress, the nature and extent of which depend upon the structure of the Y₂O₃ gate dielectric and the polarity of dc bias. With amorphous Y₂O₃, leakage currents drift to lower values under gate injection due to electron trapping, and to higher values under Si-injection due to the generation of holes. Though leakage current drift is minimal for crystalline Y₂O₃, its magnitude increases as the energy of injected electrons from mid-gap states is low and the local field due to asperity is high. The emergence of interfacial SiO₂ reduces the magnitude of Si-injection leakage current substantially, but causes transient changes resulting in switching to higher values at a threshold dc bias. Thermal detrapping of holes and reverse bias stress studies confirm that the instability of current is caused by an increase in the cathodic field from hole trapping at interface states. Leakage current instability limits the application of extrinsic high dielectric constant dielectrics in a high density DRAM storage capacitor, unless a new interface layer scheme other than SiO₂ and a method to form a defect-free dielectric layer can be implemented. Received: 29 October 2001 / Accepted: 22 April 2002 / Published online: 4 December 2002 RID="*" ID="*"Corresponding author. Fax: +1-413/545-4611, E-mail: rastogi@ecs.umass.edu     

Improved electrical properties of HfTiO/GeO x N y gate dielectric Ge MOS capacitors by using wet–NO Ge-surface pretreatment

Reactive cosputtering is employed to prepare high-permittivity HfTiO gate dielectric on n-Ge substrate. Effects of Ge-surface pretreatment on the interface and gate leakage properties of the dielectric are investigated. Excellent performances of Al/HfTiO/GeO _x N _y /n-Ge MOS capacitor with wet–NO surface pretreatment have been achieved with a interface-state density of 2.1×10¹¹ eV⁻¹ cm⁻², equivalent oxide charge of −7.67×10¹¹ cm⁻² and gate leakage current density of 4.97×10⁻⁵ A/cm² at V _g =1 V.     

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal–oxide–semiconductor capacitor

In this study, GaAs metal–oxide–semiconductor (MOS) capacitors using Y‐incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 × 10¹¹ cm^–2 eV^–1), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 × 10^–5A/cm² at V_fb + 1 V). These merits should be attributed to the complementary properties of Y₂O₃ and Ta₂O₅:Y can effectively passivate the large amount of oxygen vacancies in Ta₂O₅, while the positively‐charged oxygen vacancies in Ta₂O₅ are capable of neutralizing the effects of the negative oxide charges in Y₂O₃. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices.

Capacitance–voltage characteristic of the GaAs MOS capacitor with TaYON gate dielectric (Y content = 27.6%) proposed in this work with the cross sectional structure and dielectric surface morphology as insets.     

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g_m) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f_T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.     

Gadolinium scandate as an alternative gate dielectric in field effect transistors on conventional and strained silicon

Long channel n-type metal oxide semiconductor field effect transistors on thin conventional and strained silicon on insulator substrates have been prepared by integrating gadolinium scandate as high-κ gate dielectric in a gate last process. The GdScO₃ films were deposited by electron beam evaporation and subsequently annealed in oxygen atmosphere. Electrical characterization of readily processed devices reveals well behaved output and transfer characteristics with high I _on/I _off ratios of 10⁶–10⁸, and steep inverse subthreshold slopes down to 66 mV/dec. Carrier mobilities of 155 cm²/Vs for the conventional and 366 cm²/Vs for the strained silicon substrates were determined.     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.     

Structure and electrical properties of HfO<Subscript>2</Subscript> high-<Emphasis Type="Italic">k</Emphasis> films prepared by pulsed laser deposition on Si (100)

High-k gate dielectric hafnium dioxide films were grown on Si (100) substrate by pulsed laser deposition at room temperature. The as-deposited films were amorphous and that were monoclinic and orthorhombic after annealed at 500°C in air and N₂ atmosphere, respectively. After annealed, the accumulation capacitance values increase rapidly and the flat-band voltage shifts from −1.34 V to 0.449 V due to the generation of negative charges via post-annealing. The dielectric constant is in the range of 8–40 depending on the microstructure. The I–V curve indicates that the films possess of a promising low leakage current density of 4.2×10⁻⁸ A/cm² at the applied voltage of −1.5 V.     

Methodological aspects of the electron-beam investigation of dielectric target charging

The basic characteristics of dielectric target charging with (2–30)-keV electron beams were investigated using the example of a typical insulator, Al₂O₃. A new hypothetical scenario of dielectric charging, based on the reduction of secondary-electron current due to the formation of polarized excitons in the positive layer of a charged target, is proposed on the basis of modeling calculations and the experimental data.     

小尺寸MOSFET隧穿电流解析模型

基于表面势解析模型，通过将多子带等效为单子带，建立了耗尽/反型状态下小尺寸MOSFET直接隧穿栅电流解析模型.模拟结果与自洽解及实验结果均符合较好，表明此模型不仅可用于SiO₂、也可用于高介电常数(k)材料作为栅介质以及叠层栅介质结构MOSFET栅极漏电特性的模拟分析，计算时间较自洽解方法大大缩短，适用于MOS器件电路模拟. 关键词： 隧穿电流 MOSFET 量子机理 解析模型     

Effect of stacked dielectric with high dielectric constant and surface modification on current enhancement in pentacene thin-film transistors

The effect of a stacked dielectric has been studied on pentacene thin-film transistors (TFTs) with respect to the current enhancement, the crystalline polymorph, and the structural change of the film. Here we show that the performance improvement of the device is successfully achieved by the dielectric effects of the high dielectric constant and the surface modification in hybrid dielectric configuration. The systematic analysis on the device feature governed by the interfacial property was carried out for a hybrid structured insulator system using SiO₂ and cross-linked (C-L) polyvinyl alcohol (PVA), including the surface modified layer of dilute polymethyl methacrylate (PMMA). Through thickness combinations of bilayer dielectrics with low-k SiO₂ and high-k PVA, the device also exhibits noticeable enhancement of the current drivability up to the current level of 94 μA at a practical gate bias of ?30 V. Moreover, we present the effect of a surface-modified layer with dilute PMMA. After the formation of ultra-thin PMMA layer in a bilayer insulator, the organic dielectric shows an effectively changed surface property into hydrophobicity even on a strong hydroxyl-rich dielectric surface, resulting in the distinct increase of structural order in the film due to the reduction of surface free energy.     

A study of GaN MOSFETs with atomic-layer-deposited Al2O3 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al₂O₃ gate dielectrics are fabricated. The device, with atomic-layer-deposited Al₂O₃ as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al₂O₃ as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the Al₂O₃ film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm²/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition Al₂O₃ growth and device fabrication.     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Temperature-dependent characteristics of pulse-laser-deposited (Pb,Sr)TiO<Subscript>3</Subscript> films at low temperatures

Pulsed laser deposition (PLD) of (Pb,Sr)TiO₃ (PSrT) film on Pt/SiO₂/Si at low substrate temperatures (T_s), ranging from 300–450 °C, has been investigated. As T_s increases, the films reveal coarsening clusters, improved crystallization of the perovskite phase, distinct capacitance–electric field (C–E) hysteretic loops and a larger dielectric constant. The 350 °C-deposited film shows strong (100) preferred orientation and optimum dielectric properties with the dielectric constant of ∼620. The current density increases as the measurement temperature and the electric field increase. Moreover, PSrT films exhibit a strong negative temperature coefficient of resistance (NTCR) behavior at temperatures ranging from 100 to 390 °C. PACS 81.15.Fg; 77.22.Ch; 68.60.Dv     

Structural and dielectric properties of phosphorous-doped PLZT ceramics

In the present work we have reported the unique effects of P₂O₅-doped PLZT ceramics with composition (Pb_0.92La_0.08)(Zr_0.65Ti_0.35)O₃ +x wt% of P₂O₅ (wherex = 1, 3 and 5) prepared chemically by co-precipitation method. X-ray diffraction studies suggest that the prepared compound was very fine (10–25 nm), homogeneous and of rhombohedral symmetry. The apparent density of samples decreased with the P⁵⁺ additions. Studies of dielectric constant and dielectric loss as a function of frequency (10–1000 kHz) and temperature suggest that the compound undergoes diffuse type of phase transition without any sign of relaxor behaviour. With increasingx, dielectric constant was found to decrease appreciably, whereas Curie temperature (T_C) was found to increase     

Thermal stability and dielectric properties of ultrathin CaZrOx films prepared by pulsed laser deposition

The thermal stability and dielectric properties of amorphous CaZrO_x film prepared by pulsed laser deposition (PLD) have been investigated. X-ray diffraction (XRD) investigation shows that CaZrO_x film still remains amorphous after rapid thermal annealing at 700 °C for 10 min. Differential thermal analysis (DTA) indicates that the crystallization temperature of CaZrO_x film is about 729.53 °C, which is significantly higher than that of amorphous ZrO₂ films prepared at the similar conditions. High-resolution transmission electron microscopy (HRTEM) and X-ray photon spectroscopy (XPS) analysis reveal there exists a Si-O transition layer between the CaZrO_x film and Si substrate. The permittivity of CaZrO_x film is about 10.5 (at 1 MHz) by measuring a Pt/CaZrO_x/Pt MIM structure. Under the optimized conditions, a small EOT=0.91 nm and a leakage current density of 125 mA/cm² at 1 V gate voltage were obtained. The enhanced thermal stability and improved electrical characteristics suggest that the amorphous CaZrO_x film may be an attractive gate dielectric alternative for next generation MOS field effect transistor applications. PACS 77.55.+f; 81.15.Fg; 73.40.Qv     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.     

Electrical characteristics of Ta2O5 based capacitors with different gate electrodes

Al, W and TiN gate stacks using reactively sputtered thin (15–35 nm) Ta₂O₅ as a high-k dielectric have been investigated. It has been established that the type and the deposition technique of the gate electrode strongly affect the parameters of the structures. RF sputtered tungsten has been established as the most suitable electrode material (giving a nonreactive contact) providing a low leakage current (∼10^-8 A/cm² at 1 MV/cm) through capacitors and a high dielectric constant. The application of Al gate electrodes in the advanced DRAM devices is impeded by the chemical interaction of Al with the Ta₂O₅ films deteriorating the performance of the structures. The radiation-induced defects during the TiN deposition increase the leakage currents for TiN/Ta₂O₅/Si capacitors. A modified Poole–Frenkel conduction mechanism with a tendency for a reduction of the compensation level with increasing Ta₂O₅ thickness was found for W-gate capacitors. Schottky emission at low applied fields and modified Poole–Frenkel mechanism at high fields define the J–V characteristics of Al capacitors. The current through TiN capacitors is governed by ohmic and space charge limited conduction. The post metallization annealing in H₂ reduces the oxide charge but deteriorates both the breakdown fields and the leakage currents for all capacitors studied. The effect is stronger for Al and TiN structures and is accompanied by a reduction of the dielectric constant. PACS 72.80.Sk; 73.40.Qv; 77.55+f; 81.15 Cd     

Effect of gamma irradiation on the dielectric properties and electrical conductivity of the TlInS<Subscript>2</Subscript> single crystal

The effect of gamma irradiation on the dielectric properties and ac conductivity of a TlInS₂ single crystal with a layered structure has been investigated in the frequency range from 5 × 10⁴ to 3.5 × 10⁷Hz. It has been shown that gamma irradiation of the TlInS₂ single crystal with a dose of 10⁴–2.25 × 10⁶ rad leads to a considerable increase in the dielectric loss tangent tanδ, the real part ɛ′ and imaginary part ɛ″ of the complex permittivity, and the ac conductivity σ _ac across the layers. It has been established that, for all gamma irradiation doses, the TlInS₂ single crystal is characterized by the dielectric loss due to electrical conduction up to a frequency of 10⁷ Hz and by the relaxation loss at a higher frequency. Irradiation of the TlInS₂ single crystal results in an increase in the dispersion of tan δ, ɛ′, and ɛ″. It has been demonstrated that, as the gamma irradiation dose is accumulated in the TlInS₂ single crystal, the density of localized states near the Fermi level N _F increases (from 5.2 × 10¹⁸ to 1.9 × 10¹⁹ eV⁻¹ cm⁻³).