A survey of hardware Trojan threat and defense

Hardware Trojans (HTs) can be implanted in security-weak parts of a chip with various means to steal the internal sensitive data or modify original functionality, which may lead to huge economic losses and great harm to society. Therefore, it is very important to analyze the specific HT threats existing in the whole life cycle of integrated circuits (ICs), and perform protection against hardware Trojans. In this paper, we elaborate an IC market model to illustrate the potential HT threats faced by the parties involved in the model. Then we categorize the recent research advances in the countermeasures against HT attacks. Finally, the challenges and prospects for HT defense are illuminated.     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.     

光热辐射测量技术的三维和一维理论研究

根据连续调制激光辐照样品的一维与三维理论。并对其进行比较 ,得到无论是高热扩散率还是低热扩散率材料 ,只要频率大于 4 0Hz时 ,光热辐射测量三维理论可以用一维理论代替。及样品热扩散率越低 ,一维光热辐射测量理论和三维理论一致 ,所需要的频率就越低。这就为何时使用一维光热辐射测量理论提供依据。     

一种基于压缩边界Fisher分析的硬件木马检测方法

针对物理环境下旁路分析技术对电路中规模较小的硬件木马检出率低的问题,该文引入边界Fisher分析(MFA)方法,并提出一种基于压缩边界Fisher分析(CMFA)的硬件木马检测方法。通过减小样本的同类近邻样本与该样本以及类中心之间距离和增大类中心的同类近邻样本与异类样本之间距离的方式,构建投影空间,发现原始功耗旁路信号中的差异特征,实现硬件木马检测。AES加密电路中的硬件木马检测实验表明,该方法具有比已有检测方法更高的检测精度,能够检测出占原始电路规模0.04%的硬件木马。     

导波结构三维不连续性问题的高次六面体边缘元分析

该文从全磁场矢量泛函出发,讨论了一种54参量六面体边缘元的空间构造。这种高次三维边缘元方法不但有效地消除了伪解,而且具有很高的计算精度。用这种方法对导波结构三维不连续性散射问题的分析,证实了它的有效性和可靠性。与12参量六面体边缘元计算结果的比较表明:本文方法具有更高的精度和计算效率,是一种求解三维不连续性问题的高效数值方法,有着推广应用的实际价值。     

基于PC机的断层图象序列3-D表面重建

由断层图象序列重建三维物体模型及其可见表面显示是目前国际上十分活跃的研究课题。本文对X射线CT图象序列重建三维对象模型,以及可见表面3-D显示进行了研究。提出一种给定分段点数的轮廓多边形近似方法,继而提出一种快速断面图象间轮廊插值方法。对重建出的人体肝脏体元阵列,用深度和梯度明暗显示方法进行显示,肝脏可见表面的3-D显示结果令人满意。全部软件都是在以PC/AT为主机,配以PC-VISION图象处理板的微机图象处理系统上,用C语言编程实现的。     

基于路径特征和支持向量机算法的硬件木马检测技术

硬件木马攻击成为当前集成电路(IC)面临的严重威胁。针对硬件木马电路具有隐蔽、不易触发以及数据集不均衡等特点,该文提出对门级网表进行静态分析的硬件木马检测技术。基于电路可测性原理建立涵盖节点扇入数、逻辑门距离、路径数、节点扇出数的硬件木马路径特征,简化特征分析流程;基于提取的路径特征,使用支持向量机(SVM)算法区分电路中的木马节点和正常节点。提出训练集双重加权技术,解决数据集不均衡问题,提升分类器的性能。实验结果表明,分类器可以用于电路中的可疑节点检测,准确率(ACC)达到99.85%;训练集静态加权有效提升分类器性能,准确率(ACC)提升5.58%;与现有文献相比,以36%的特征量,真阳性率(TPR)降低1.07%,真阴性率(TNR)提升2.74%,准确率(ACC)提升2.92%。该文验证了路径特征和SVM算法在硬件木马检测中的有效性,明确了数据集均衡性与检测性能的关系。     

一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现

硬件木马检测已成为当前芯片安全领域的研究热点,现有检测算法大多面向ASIC电路和FPGA电路,且依赖于未感染硬件木马的黄金芯片,难以适应于由大规模可重构单元组成的粗粒度可重构阵列电路。因此,该文针对粗粒度可重构密码阵列的结构特点,提出基于分区和多变体逻辑指纹的硬件木马检测算法。该算法将电路划分为多个区域,采用逻辑指纹特征作为区域的标识符,通过在时空两个维度上比较分区的多变体逻辑指纹,实现了无黄金芯片的硬件木马检测和诊断。实验结果表明,所提检测算法对硬件木马检测有较高的检测成功率和较低的误判率。     

家用3-D电视端到端标准开发的综述

消费者对于近期的3-D放映活动反应非常热烈,这证明了使用者对3-D内容的渴望,3-D似乎注定要成为家庭娱乐产业的下一代杀手级应用。到那时,3-D格式的母版后期处理及发行标准对于其在消费市场的成功推广是极其重要的。     

SVM算法在硬件木马旁路分析检测中的应用

集成电路(ICs)面临着硬件木马(HTs)造成的严峻威胁。传统的旁路检测手段中黄金模型不易获得,且隐秘的木马可以利用固硬件联合操作将恶意行为隐藏在常规的芯片运行中,更难以检测。针对这种情况,该文提出利用机器学习支持向量机(SVM)算法从系统操作层次对旁路分析检测方法进行改进。使用现场可编程门阵列(FPGA)验证的实验结果表明,存在黄金模型时,有监督SVM可得到86.8%的训练及测试综合的平均检测准确率,进一步采用分组和归一化去离群点方法可将检测率提升4%。若黄金模型无法获得,则可使用半监督SVM方法进行检测,平均检测率为52.9%～79.5%。与现有同类方法相比,验证了SVM算法在指令级木马检测中的有效性,明确了分类学习条件与检测性能的关系。

     

3-D自由立体显示的性能表征

三维自由立体显示的图像生成和参数显示与一般的二维显示不同,需要其它的方法来校验光学性能。目前工业上缺少标准化的三维显示测试方法,报道过的测量结果可能不具有可比性,因此需要建立标准化的测试方法,而且这个方法的计量和度量必须适用于任何一种特定的立体显示技术。文中探索了对自由立体显示技术进行表征的一些方法。     

FINFET的三维模拟

采用三维模拟软件对具有FINFET结构的SOI-MOSFET进行了模拟.研究了FINFET的I-V特性、亚阈值特性、短沟道效应等.模拟发现,通过降低fin的高度可以有效地抑制短沟道效应与提高器件的性能,因此fin的高度是器件设计中一个关键参数.模拟结果表明FINFET在特性上优于传统的单栅器件.     

立体显示器中的三维构图解析

由于立体显示器日益普及,因此相关立体显示器要展现出真实且令人印象深刻的三维立体图形或场景前所未有地变得重要。文中回顾了时下观看者从立体显示器中获得三维构图立体感的有关研究工作。     

近场数字摄影测量技术在三维测量中的应用

基于近场数字摄影测量术建立了用于三维测量的工业视觉系统。本文介绍了近场摄影测量原理、测量系统定标、测量实验及结果,提出用最小二乘的广义逆法求解非线性方程组解决系统的畸变问题。     

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.     

3-D Epanechnikov Mixture Regression in integral imaging compression

Integral imaging is a kind of 3D display with no glasses, which represents the future developments. Elementary image array (EIA) is an essential component of integral imaging. Our coding framework includes pre-processing, modeling, and reconstruction. We acquire the sub-EIA from the original EIA and get the offsets between adjacent elementary images (EIs) through pre-processing. As for modeling, we get the optimal combination of 3-D Epanechnikov Mixture Regression (3-D EMR) or 3-D Gaussian Mixture Regression (3-D GMR) by Elementary Image Adaptive Model Selection (EI-AMLS) algorithm to achieve the best modeling of sub-EIA. Finally, the linear-based reconstruction is completed according to the correlation between adjacent EIs. Our decoded images realize a clearer outline reconstruction and more superior coding efficiency than HEVC and JPEG2000 below about 0.05bpp. Furthermore, the proposed method can achieve the same visual effect as HEVC with only 15% to 80% time consumed.     

三维（3—D）封装技术

3-D多芯片组件（MCM）是未来微电子封装的发展趋势。本文介绍了超大规模集成（VLSI）用的3-D封装技术的最新进展,详细报导了垂直互连技术,概括讨论了选择3-D叠层技术的一些关键问题,并对3-D封装和2-D封装及分立器件进行了对比。     

水下激光距离选通三维成像方法

基于水下距离选通激光成像技术,利用选通成像中回波强度相变化特性中包含的距离信息,提出了一种针对水下目标的三维成像方法。结合实验室现有的水下距离选通激光成像系统,对15 m处的水下目标进行了三维成像。这一方法有效抑制了水下成像系统中存在的目标表面材质、水体衰减以及目标各点法线方向与入射激光脉冲方向夹角不同等因素对于三维成像造成的不良影响,同时仅需要从单一方向对目标进行成像,减少了所需图像采集的次数,简化了三维重构的过程。     

三维微结构制作现状与进展

随着微机电系统(MEMS)的深入研究和快速发展,三维微细加工技术对于微机电的开发和生产具有非常重要的意义.详细介绍了现阶段三维微结构各种制作方法和工艺技术,分析了其原理和特点,比较了各种方法的优劣;讨论了三维微结构开发现状及有待解决的关键技术,综述了利用电子束曝光技术进行三维微结构制作的应用现状并指出了其发展前景.