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根据视频流与实时监视应用的特点,提出一种基于TCP协议的动态双缓冲与双线程视频实时传输算法。在发送方设置视频数据缓存与数据发送缓存,并分别由视频数据输入线程与视频数据发送线程负责管理;视频数据输入线程根据预设的最大等待发送时间与实时计算的网络传输速率,动态调节缓存的大小以及在网络拥塞时有选择性地丢弃视频帧;视频数据发送线程实现视频数据发送与按帧从视频数据缓存获取数据,并实时计算出网络数据传输速率。实验结果表明,本算法能最大限度地利用动态变化的网络带宽,保证视频实时发送至接收方与平稳播放,可有效地应用于窄变带宽网络环境下实时视频监视。 相似文献
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随着用户和网络规模的快速扩大以及精细化运营需求的增加,网络流量分析系统面临的数据规模及分析深度要求都在快速发展,针对传统技术在系统扩展性、建设成本以及分析深度方面已经很难满足目前需求这一问题,提出了一种基于MapReduce 技术的大规模流量分析系统技术方案,对数据存储、数据分析全部并行化处理,消除传统系统存在的若干瓶颈。 相似文献
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随着移动通信日益普及,用户对服务品质和性能的要求也越来越高。话音业务作为用户最基本的业务,是评价用户感知质量的最重要方面。如何客观评估话音质量,高效地发现现网话音业务中存在的问题,定位问题的产生原因,都是移动通信网络维护面临的新课题。本文研究的内容,就是通过分析现网的话音媒体流,对用户通话的质量进行评估,定位话音降质的故障原因及故障点,并使媒体流的分析能够结合实际工作的需要,提供与话音质量相关的核心网、无线网支撑服务,即研究网络改造解决新方案。 相似文献
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Parallel Scalability of Video Decoders 总被引:1,自引:0,他引:1
Cor Meenderinck Arnaldo Azevedo Ben Juurlink Mauricio Alvarez Mesa Alex Ramirez 《Journal of Signal Processing Systems》2009,57(2):173-194
An important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level
parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs) are expected to contain. As a case study
we investigate the parallelism available in video decoders, an important application domain now and in the future. Specifically,
we analyze the parallel scalability of the H.264 decoding process. First we discuss the data structures and dependencies of
H.264 and show what types of parallelism it allows to be exploited. We also show that previously proposed parallelization
strategies such as slice-level, frame-level, and intra-frame macroblock (MB) level parallelism, are not sufficiently scalable.
Based on the observation that inter-frame dependencies have a limited spatial range we propose a new parallelization strategy,
called Dynamic 3D-Wave. It allows certain MBs of consecutive frames to be decoded in parallel. Using this new strategy we
analyze the limits to the available MB-level parallelism in H.264. Using real movie sequences we find a maximum MB parallelism
ranging from 4000 to 7000. We also perform a case study to assess the practical value and possibilities of a highly parallelized
H.264 application. The results show that H.264 exhibits sufficient parallelism to efficiently exploit the capabilities of
future manycore CMPs.
Cor Meenderinck received the MSc degree in electrical engineering from Delft University of Technology, the Netherlands. Currently, he is working toward the PhD degree in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, the Netherlands. His research interests include computer architecture, chip multi-processors, media accelerators, design for power efficiency, design for variability, computer arithmetic, nano electronics, and single electron tunneling. Arnaldo Azevedo received the BSc degree in computer science from the UFRN University, Natal, RN, Brazil, in 2004 and the MSc degree in computer science from UFRGS University, Porto Alegre, RS, Brazil, in 2006. Since 2006, he is a doctoral candidate in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, the Netherlands. He is currently investigating multimedia accelerators architecture for multi-core processors. Ben Juurlink is an associate professor in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics, and Computer Science at Delft University of Technology, the Netherlands. He received the MSc degree in computer science, from Utrecht University, Utrecht, the Netherlands, in 1992, and the Ph.D. degree also in computer science from Leiden University, Leiden, the Netherlands, in 1997. His research interests include instruction-level parallel processors, application-specific ISA extensions, low power techniques, and hierarchical memory systems. He has (co-) authored more than 50 papers in international conferences and journals and is a senior member of the IEEE and a member of the ACM. Mauricio Alvarez Mesa received the BSc degree in electronic engineering from University of Antioquia, Medellin, Colombia in 2000. From 2000 to 2002 he was a teaching assistant at Department of Electronic Engineering of the this University. In 2002 he joined the High Performance Computing Group at the Computer Architecture Department of the Technical University of Catalonia (UPC) where he is doing his PhD. From 2006 he became teaching assistant at UPC. He was a summer student intern at IBM Haifa Research labs, Israel in 2007. His research interest includes high performance architectures for multimedia applications, vector processors, SIMD extensions, multicore architectures and streaming architectures. Alex Ramirez is an associate professor in the Computer Architecture Department at the Universitat Politecnica de Catalunya, and leader of the Computer Architecture group at BSC. He has a BSc (’95), MSc (’97) and PhD (’02, awarded the UPC extraordinary award to the best PhD in computer science) in computer science from the Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. He has been a summer student intern with Compaq’s WRL in Palo Alto, California for two consecutive years (’99–’00), and with Intel’s Microprocessor Research Laboratory in Santa Clara (’01). His research interests include compiler optimizations, high performance fetch architectures, multithreaded architectures, and vector architectures. He has coauthored over 50 papers in international conferences and journals and supervised 3 PhD students. 相似文献
Alex RamirezEmail: |
Cor Meenderinck received the MSc degree in electrical engineering from Delft University of Technology, the Netherlands. Currently, he is working toward the PhD degree in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, the Netherlands. His research interests include computer architecture, chip multi-processors, media accelerators, design for power efficiency, design for variability, computer arithmetic, nano electronics, and single electron tunneling. Arnaldo Azevedo received the BSc degree in computer science from the UFRN University, Natal, RN, Brazil, in 2004 and the MSc degree in computer science from UFRGS University, Porto Alegre, RS, Brazil, in 2006. Since 2006, he is a doctoral candidate in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, the Netherlands. He is currently investigating multimedia accelerators architecture for multi-core processors. Ben Juurlink is an associate professor in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics, and Computer Science at Delft University of Technology, the Netherlands. He received the MSc degree in computer science, from Utrecht University, Utrecht, the Netherlands, in 1992, and the Ph.D. degree also in computer science from Leiden University, Leiden, the Netherlands, in 1997. His research interests include instruction-level parallel processors, application-specific ISA extensions, low power techniques, and hierarchical memory systems. He has (co-) authored more than 50 papers in international conferences and journals and is a senior member of the IEEE and a member of the ACM. Mauricio Alvarez Mesa received the BSc degree in electronic engineering from University of Antioquia, Medellin, Colombia in 2000. From 2000 to 2002 he was a teaching assistant at Department of Electronic Engineering of the this University. In 2002 he joined the High Performance Computing Group at the Computer Architecture Department of the Technical University of Catalonia (UPC) where he is doing his PhD. From 2006 he became teaching assistant at UPC. He was a summer student intern at IBM Haifa Research labs, Israel in 2007. His research interest includes high performance architectures for multimedia applications, vector processors, SIMD extensions, multicore architectures and streaming architectures. Alex Ramirez is an associate professor in the Computer Architecture Department at the Universitat Politecnica de Catalunya, and leader of the Computer Architecture group at BSC. He has a BSc (’95), MSc (’97) and PhD (’02, awarded the UPC extraordinary award to the best PhD in computer science) in computer science from the Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. He has been a summer student intern with Compaq’s WRL in Palo Alto, California for two consecutive years (’99–’00), and with Intel’s Microprocessor Research Laboratory in Santa Clara (’01). His research interests include compiler optimizations, high performance fetch architectures, multithreaded architectures, and vector architectures. He has coauthored over 50 papers in international conferences and journals and supervised 3 PhD students. 相似文献
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Yung-Chi Chang Chih-Wei Hsu Wei-Min Chao Liang-Gee Chen 《The Journal of VLSI Signal Processing》2006,44(1-2):117-134
Video streaming with varying transmission bandwidth is becoming increasingly important. In this paper, an interactive video
streaming system is proposed. Fine Granularity Scalability (FGS) is applied to be the streaming video format. The computational
complexity of FGS coding is analyzed to explore an efficient FGS implementation. A new transmission model is proposed for
the realization of a content-aware video streaming. At encoder side, the current MPEG-4 FGS coding flow is reordered such
that the picture-level maximum can be acquired in advance and bit-plane data can be dynamically adapted. With these proposed
hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to achieve a cost-effective
solution to FGS implementation. The streaming server can adaptively decide quality-enhanced region by selective enhancement
according to both object information from encoding side and user-defined region from receiver side. From the simulation results,
it’s demonstrated that the proposed approach can provide better quality in users’ interest regions with no bit-rate or complexity
overhead.
Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S., M.S., and Ph.D. degrees from the Department of Electrical
Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998, 2000, and 2005, respectively. He serves as senior
engineer in SoC Solutions Dept., Vivotek Inc. now. His research interests include video coding algorithms and VLSI architectures
for image/video processing.
Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei,
in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits
related to multimedia coding standard and digital consumer devices. His research interests include video coding, video processing
and VLSI design.
Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering,
National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture
for image and video processing.
Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National
Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate
Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service
during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In
1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting
Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of
Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate
Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department
of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics and Optoelectronics
Research Laboratories in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP
architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE
Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems
since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate
Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video
Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of
the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation.
He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical
Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the
IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS
Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the
IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to
1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference
on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society.
In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence
Award from Acer. He is a member of Phi Tan Phi. 相似文献
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基于Spark平台的NetFlow流量分析系统 总被引:1,自引:0,他引:1
目前典型的NetFlow分析系统多为基于私有架构或平台的第三方系统,面临扩展性较低、开放性不足、扩容代价大、分析时延长等问题.大数据技术的快速发展尤其是内存式计算平台如Spark的出现为集中处理大规模NetFlow数据提供了可能,本文提出了基于Spark的NetFlow分析系统,验证了核心算法(如流量应用构成统计)在Spark平台的性能.实验表明,基于Spark的NetFlow分析系统具有很高的性能和很强的扩展能力,较之Hadoop MapReduce有显著的性能提升. 相似文献
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扩展性是衡量高性能并行系统的一个关键要素,而扩展性的研究主要集中在同构的高性能系统上,异构系统研究的文献很少. 本文以异构系统为研究对象,根据实际应用任务,将计算任务分为三类:单任务模型、元任务池模型和fork-join任务队列模型,并给出这三类计算任务的定义. 提出描述基于计算任务和体系结构相匹配的异构计算系统匹配矩阵,给出异构计算的可扩展性定义. 针对上述三种计算任务模型以及异构匹配给出异构系统的可扩展性条件,为异构系统的可扩展性提供了理论依据. 用实例分析证实了这种方法的有效性. 相似文献
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MPLS是最成功地把IP和ATM融合到一起的技术之一.对基于ATM的MPLS域的扩展性进行研究,介绍了改善 MPLS网络扩展性的几种方法,并重点对VC合并机制进行讨论. 相似文献
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基于MATLAB的大规模电路稳态分析 总被引:1,自引:0,他引:1
借助于MATLAB语言强大的矩阵变换与运算功能,利用混合节点法编制含有理想电压源和受控源的大规模电路稳态分析程序。程序具有通用自由的输入格式和直观形象的输出形式,为大规模线性电路稳态分析提供了一个便利且有效的辅助工具。文章介绍了程序总体框图和编程要点,最后给出应用实例,经分析得到各节点电压和各支路电流,并给出相应的相量图和时域波形图。 相似文献