Parallel architectures for image processing

Image processing is often considered a good candidate for the application of parallel processing because of the large volumes of data and the complex algorithms commonly encountered. This paper presents a tutorial introduction to the field of parallel image processing. After introducing the classes of parallel processing a brief review of architectures for parallel image processing is presented. Software design for low-level image processing and parallelism in high-level image processing are discussed and an application of parallel processing to handwritten postcode recognition is described. The paper concludes with a look at future technology and market trends     

Fast Hartley transforms for image processing

The fast Hartley transform (FHT) is used to transform two-dimensional image data. Because the Hartley transform is real-valued, it does not require complex operations. Both spectra and autocorrelations of two-dimensional ultrasound images of normal and abnormal livers were computed     

Integer sinusoidal transforms for image processing

The sine and cosine transforms, which are popular transforms for image coding, are members of a sinusoidal transform family. Each member of the family is the optimal KLT of a Markov process. This paper derives the conditions under which the order-8 sinusoidal transforms can be approximated by orthogonal integer transforms which can be implemented using integer arithmetic. Some integer transforms are derived as examples. The results show that for the popular even sine-1, even sine-2 and the cosine transforms, there is an infinite number of integer transforms and some have their transform component magnitudes less than eight. In LSI implementation, if low implementation cost and fast computation speed are paramount, then an integer transform of small component magnitudes can be chosen. If better performance is desired, integer transforms whose elements have larger magnitudes can be used. The availability of many integer transforms provides a design engineer the freedom to trade-off performance against simple implementation and speed.     

Multichannel transforms for signal/image processing

This paper presents a novel approach to the Fourier analysis of multichannel time series. Orthogonal matrix functions are introduced and are used in the definition of multichannel Fourier series of continuous-time periodic multichannel functions. Orthogonal transforms are proposed for discrete-time multichannel signals as well. It is proven that the orthogonal matrix functions are related to unitary transforms (e.g., discrete Hartley transform (DHT), Walsh-Hadamard transform), which are used for single-channel signal transformations. The discrete-time one-dimensional multichannel transforms proposed in this paper are related to two-dimensional single-channel transforms, notably to the discrete Fourier transform (DFT) and to the DHT. Therefore, fast algorithms for their computation can be easily constructed. Simulations on the use of discrete multichannel transforms on color image compression have also been performed.     

Modular design methodologies for image processing architectures

A methodology for the design of modular and optimized architectural blocks for the generation of local windows of pixels is presented. The proposed formalization and the related techniques follow a design approach derived from the window-based algorithmic decomposition of low- and medium-level image processing algorithms     

General logarithmic image processing convolution.

The logarithmic image processing model (LIP) is a robust mathematical framework, which, among other benefits, behaves invariantly to illumination changes. This paper presents, for the first time, two general formulations of the 2-D convolution of separable kernels under the LIP paradigm. Although both formulations are mathematically equivalent, one of them has been designed avoiding the operations which are computationally expensive in current computers. Therefore, this fast LIP convolution method allows to obtain significant speedups and is more adequate for real-time processing. In order to support these statements, some experimental results are shown in Section V.     

Computer architectures for image processing in the USA

Innovative computer architectures have been developed to meet the high speed computation needs of image processing applications. These architectures take advantage of the highly structured characteristics of image data and image processing algorithms. In this paper several alternative architectures for image processing are discussed and some current hardware development projects in the USA are described. Two established computer architectures for image processing are highly parallel binary array processing and pipeline processing. Current designs involving these architectures make good use of Large Scale Integration technology. New emerging architectures, which are still in the development stage, include multi-microprocessor systems and analog processors based on charge coupled devices.     

Multiscale recursive medians, scale-space, and transforms withapplications to image processing

A cascade of increasing scale, 1-D, recursive median filters produces a sieve, termed an R-sieve, has a number of properties important to image processing. In particular, it (1) Simplifies signals without introducing new extrema or edges, that is, it preserves scale-space. It shares this property with Gaussian filters, but has the advantage of being significantly more robust. (2) The differences between successive stages of the sieve yield a transform, to the granularity domain. Patterns and shapes can be recognized in this domain using idempotent matched sieves and the result transformed back to the spatial domain. The R-sieve is very fast to compute and has a close relationship to 1-D alternating sequential filters with flat structuring elements. They are useful for machine vision applications.     

VLSI architectures for discrete wavelet transforms

A folded architecture and a digit-serial architecture are proposed for implementation of one- and two-dimensional discrete wavelet transforms. In the one-dimensional folded architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded architecture is minimized by the use of a generalized life time analysis. The converter units are synthesized with a minimum number of registers using forward-backward allocation. The advantage of the folded architecture is low latency and its drawbacks are increased hardware area, less than 100% hardware utilization, and the complex routing and interconnection required by the converters used. These drawbacks are eliminated in the alternate digit-serial architecture at the expense of an increase in the system latency and some constraints on the wordlength. In latency-critical applications, the use of the folded architecture is suggested. If latency is not so critical, the digit-serial architecture should be used. The use of a combined folded and digit-serial architecture is proposed for implementation of two-dimensional discrete wavelet transforms     

Signal and image processing using three-dimensional binary ranking transforms

Because binary mathematical morphology permits fast local neighborhood operations by flash conversion, it is used extensively in high-speed pattern-recognition computer systems. Further, since anyN-dimensional integer function may be represented by an (N + 1)-dimensional binary (bilevel) function, ordinary two-dimensional graylevel images become three-dimensional binary images. Thus these images may be processed by high-speed flash-conversion computers assuming that a sufficiently compact three-dimensional kernel can be devised. The tetradekahedron of the face-centered-cubic tessellation forms a perfect kernel in three-dimensions. Its neighborhood is compact. It has total symmetry with all 12 neighbors equidistant from the central element. Using this kernel a variety of useful three-dimensional morphological operations may be performed for target track detection, shaded graphics, data clustering, automated focusing, and spatial filtering.This research was supported by the National Cancer Institute (Grant CA45047), the National Science Foundation (Grant DCR8611863), the Office of Naval Research (Contract Number N001488K-0435-N143), and the Department of Defense (delivery order 00055, San Diego State University Foundation, under Contract 85-D0203 from the Naval Ocean Systems Center).     

FPGA implementations of fast Fourier transforms for real-time signal and image processing

Applications based on the fast Fourier transform (FFT), such as signal and image processing, require high computational power, plus the ability to experiment with algorithms. Reconfigurable hardware devices in the form of field programmable gate arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. However, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. They do not therefore facilitate easy development of, or experimentation with, signal/image processing algorithms. To try to reconcile the dual requirements of high performance and ease of development, the paper reports on the design and realisation of a high level framework for the implementation of 1D and 2D FFTs for real-time applications. A wide range of FFT algorithms, including radix-2, radix-4, split-radix and fast Hartley transform (FHT) have been implemented under a common framework in order to enable system designers to meet different system requirements. Results show that the parallel implementation of 2D FFT achieves linear speed-up and real-time performance for large matrix sizes. Finally, an FPGA-based parametrisable environment based on 2D FFT is presented as a solution for frequency-domain image filtering application.     

An improved recursive median filtering scheme for image processing

In a recent publication, it was shown that median filtering is an optimization process in which a two-term cost function is minimized. Based on this functional optimization property of the median filtering process, a new approach for designing the recursive median filter for image processing applications is introduced in this paper. We prove that the new approach is guaranteed to converge to root within a finite number of iterations. The new method is applied to process a real image corrupted by pseudorandom impulsive noise, and the results show that the new scheme provides improved mean square error (RISE) performance over the standard recursive median filters.     

A Truncation method for computing slant transforms withapplications to image processing

A truncation method for computing the slant transform is presented. The slant transform truncation (STT) algorithm uses the divide and conquer principle of hierarchical data structures to factorize coherent image data into sparse subregions. In one dimension with a data array of size N=2ⁿ, the truncation method takes a time between O(N) and O(Nlog₂N), degenerating to the performance of the fast slant transform (FST) method in its worst case. In two dimensions, for a data array of size N×N, the one-dimensional truncation method is applied to each row, then to each column of the array, to compute the transform in a time between O(N²) and O(N²log₂N). Coherence is a fundamental characteristic of digital images and so the truncation method is superior to the FST method when computing slant transforms of digital images. Experimental results are presented to justify this assertion     

Fast number-theoretic transforms for digital filtering

A special number-theoretic transform that can be computed, using a high-radix fast Fourier transform, is defined on primes of the form (2n ? 1) 2n +1. Methods for finding these primes and the primitive dth roots of unity in a field modulo such primes are also included.     

Algorithm for linear convolution using number theoretic transforms

A linear convolution of two N-point sequences is computed by using N-point Fermat number transforms, so that the convolution length is doubled for a given modulo Fermat number. The algorithm is also suitable for other convolutional algorithms of number theoretic transforms     

Pipelined systolic architectures for DLMS adaptive filtering

This work reports two new pipelined, systolic architectures for delayed least mean squares (DLMS) adaptive filtering. In contrast to existing systolic architectures, which introduce a tracking delay that increases linearly with filter order, those presented here, do not. They support the same sampling rate as the fastest such architecture reported so far, even when unpipelined. Our designs use significantly less hardware (i.e., multiply-accumulate modules and registers) with minimal control logic requirement on account of the algebraic projection techniques that we employ, implying a net gain in terms of the silicon area utilized and the dynamic power dissipated. Further, one of these architectures introduces only half the adaptation delay that is conventionally used for systolization; the other requires the normal adaptation delay, but compensates by using considerably reduced control logic. The sampling rates supported by our architectures are further increased by pipelining the processor modules to the level of a 42 compressor. This requires only small adaptation and tracking delays, which are independent of filter order, and is possible without requiring a modification of the basic algorithm (in terms of introducing a lookahead in the adaptation), all in contrast with the only pipelined DLMS architecture reported so far. We propose and implement a scheme in our architectures, for computing a normalized step size for delayed adaptation, in the general context of a nonstationary real-time environment. The simulation studies performed with our architectures indicate remarkably improved convergence properties over those of previously reported architectures.     

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.     

基于同态滤波的电子散斑干涉图像处理

由于散斑具有可测的强度和确定的相位,正逐渐被人们重视和进一步研究,现广泛应用于无损检测领域。电子散斑干涉条纹图上总是附带大量的随机散斑颗粒噪声。一般来说,散斑图像记录的变形信息主要集中在低频部分,而噪声主要在高频部分。为了得到变形物体的连续相位分布,需要用适当的方法对散斑干涉条纹图像进行滤波降噪处理。同态滤波是一种将亮度范围压缩和对比度增强的频域处理方法。采用基于同态滤波原理设计出的新的低通滤波器,将其运用于3步相移电子散斑干涉条纹图像处理,并从理论上进行了详细的论述。结果表明,运用该滤波器处理散斑条纹图像,过滤了大量的散斑颗粒噪声,增强了散斑干涉条纹的对比度。     

局部标准差滤波在图像处理中的应用

为了在抑制噪声的同时尽可能保留图像边缘等重要信息,提出了一种局域标准差滤波器设计方法.该方法通过计算滤波器窗口中每一像素点的局域标准差,然后通过确定最小局域标准差对应像素点,使之作为滤波器的输出.仿真实验表明,提出的局域标准差滤波器具有很强的噪声抑制和边缘保持能力.