一种采用半速结构的CMOS串行数据收发器的设计

设计了一种单片集成的CMOS串行数据收发器．该收发器用于线上速率为1.25Gb/s的千兆以太网中,全集成了发送和接收的功能,主要由时钟发生器、时钟数据恢复电路、并串／串并转换电路、线驱动器和均衡器组成．为了降低系统设计难度和电路功耗,收发器采用了半速率时钟结构．电路采用1.8V 0.18μm 1P6M CMOS数字工艺,芯片面积为2.0mm×1.9mm．经Cadence Spectre仿真验证以及流片测试,电路工作正常,功能良好．     

一种采用半速率时钟的1.25Gbit/s串行数据接收器的设计

介绍了一种用于接收1.25Gbit/s不归零随机数据的吉比特以太网接收器的设计。该电路采用半速率时钟结构,目的是为了以较低的功耗和简单的结构适应高速数据流。本文介绍了电路的主要组成部分和工作原理,突出了关键模块的设计。电路采用1.8V 0.18祄 1P6M CMOS工艺,经SpectreS仿真验证以及流片测试,主要功能已经实现。     

一种适用于高速串行数据通信的发送器

介绍了一种采用深亚微米CMOS工艺实现的单片集成发送器的设计.该发送器适用于高速串行硬盘接口,主要由时钟发生器、并串转换电路和片内阻抗匹配的线驱动器三大模块组成.发送器采用0.18μm六层金属单层多晶N阱CMOS工艺实现,芯片面积1.3mm×0.78mm.测试结果表明时钟发生器可工作在1.5GHz的频率下,数据可以正常发送.发送器总体功耗为95mW,输出共模电平270mV,单端输出幅度270mV.     

一种适用于高速串行数据通信的发送器

介绍了一种采用深亚微米CMOS工艺实现的单片集成发送器的设计.该发送器适用于高速串行硬盘接口,主要由时钟发生器、并串转换电路和片内阻抗匹配的线驱动器三大模块组成.发送器采用0 .18μm六层金属单层多晶N阱CMOS工艺实现,芯片面积1.3mm×0 .78mm .测试结果表明时钟发生器可工作在1.5 GHz的频率下,数据可以正常发送.发送器总体功耗为95 m W,输出共模电平2 70 m V ,单端输出幅度2 70 m V.     

一种高速串行数据接收芯片的设计

文章设计了一种用于光纤通信的高速串行数据接收芯片。本芯片采用0．6μm BiCMOS工艺实现．最高工作频率为400M~，主要由时钟数据恢复、串并转换、10B/B解码等电路构成。在设计中，采用了双PI工环路、全差分拓扑结构、负阻放大电路与运放级联等结构，有效地减小了功耗及噪声，且用Cadence软件进行了仿真验证。     

应用于高速串行收发器的CDR电路的设计

时钟数据恢复(CDR)电路是高速数据传输系统的重要组成部分.文章介绍了一种半数字二阶时钟数据恢复电路的基本结构、工作原理和设计方法,并进行了仿真和验证,结果表明,电路能够满足系统设计要求.     

100 Base-Tx以太网物理收发器的设计

介绍了与当今100 Ms/s以太网兼容的100Base-Tx物理收发器的设计.描述了信道特性和系统的结构,详细阐述了各模块,尤其是线驱动器和接收器,的设计.最后给出了整体仿真结果,并对如何进行数模混合仿真进行了讨论.     

一种双通道UART的设计

为了满足串行通信中高速率、低错误率和多路传输的要求,通过采用过采样技术和一种比传统的组合逻辑电路快捷高效的时序电路奇偶校验方法,设计了使用更加灵活方便的双通道通用异步收发器（DUART）。仿真结果表明电路达到设计要求,并完成了版图设计。     

基于FPGA的UART模块的设计

为了实现计算机与基于FPGA图像处理系统的数据通信,这里用FPGA设计了一款简易通用异步收发器(UART)模块.UART的主要功能是实现数据处理模块与RS 232串行数据接口之间的数据转换,即将送过来的并行数据转换为输出的串行数据流,由数据处理模块传送给计算机,还可以将串行数据转换为并行数据,供数据处理模块使用.为了简化电路设计,减少电路面积,这里省略了UART系统中的奇偶检验模块.     

一种误码率为10-12的750MHz半数字结构时钟和数据恢复电路的研究

A semi-digital clock and data recovery (CDR) is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1P8M CMOS process, our CDR is integrated into a high speed serial and de-serial (SERDES) chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

A CMOS 4-Element Ku-Band Phased-Array Transceiver

This paper presents a Ku-Band fully differential 4-element phased-array transceiver using a standard 180-nm CMOS process. Each transceiver is integrated with a 5-bit phase shifter and 4-bit attenuator for high-resolution radiation manipulation. The front-end system adopts time-division mode, and hence two low-loss T/R switches are included in each channel. At room temperature, the measured root-mean-square(RMS) phase error is less than 5.5°. Furthermore, the temperature influence on passive swit...     

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively     

用串行通信口与无线收发模块实现无线数据传输台

文章介绍了一种用微机串行通信口和无线收发模块无线数传电台中心点处的电路。该电路结构简单可靠 ,并可以根据实际需要 ,更换有关器件 ,来满足不同速率或不同距离的数据传输。文章给出了电路各部分的电路图或原理图。     

用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2.4GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0.35μm CMOS工艺技术,在2V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3mA,输入三阶截距点达到20dBm,输出的信号幅度为87mV;下混频器消耗的电流为3.5mA,得到的转换增益是20dB,输入参考噪声电压是6.5nV/ Hz,输入三阶截距点为4.4dBm.     

用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2 .4 GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0 .35μm CMOS工艺技术,在2 V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3m A,输入三阶截距点达到2 0 d Bm ,输出的信号幅度为87m V;下混频器消耗的电流为3.5 m A,得到的转换增益是2 0 d B,输入参考噪声电压是6     

A 0.25-μm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture

We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-mum CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-N frequency synthesizer achieves seamless handover with a 25 mus channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides -105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm² and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply     

WiMax终端收发系统结构分析

概述IEEE802.16/wiMax规范及演变, 对IEEE802.16/WiMax的射频接收器的结构和性能进行了系统分析,并介绍了几种芯片组的解决方案.     

毫米波CMOS集成电路收发机前端研究进展

对毫米波CMOS集成电路收发机前端技术进行了综述。介绍了毫米波CMOS集成电路收发机的研究背景,分别对毫米波CMOS集成电路收发机前端各个子模块进行了详细介绍和比较,并展望了毫米波CMOS集成电路的未来发展方向。