A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations

This paper presents a current driver with a novel high voltage (HV) switch schematic for the use as a protective switch for recording circuits during the stimulation sequence in neural measurement system. The current driver can source and sink currents of amplitudes up to ±8.2 mA with a HV tolerance from 30 V up to 120 V. The proposed HV switch also tolerates the voltage difference up to 120 V between its terminals. Between stimulation sequences the driver provides the effective isolation of the stimulation electrode from ground and HV supply voltage. The inter pulse current is no more than 60 pA. The chip was fabricated with AMS HV 0.35 \(\mu\)m CMOS technology. For test purposes the complete stimulation system including the proposed chip and the external C8051F410 controller was build. For the proposed system the mismatch between the sourced and sinked current does not exceed 20 \(\mu\)A. The possibility to stimulate with frequencies up to 1 kHz is proven by measurement along with the electrode-tissue model.     

A low-power 2/5.8-GHz dual-wide-band CMOS LC-VCO with switched-inductor technique

A fully integrated dual-band LC voltage control oscillator, designed in a 0.18-µm CMOS technology for 5.8-GHz/2.0-GHz wireless communication applications, is described. The frequency band switching is accomplished with switched-inductor technique. The dual-band oscillator can be operated in 5.38–6.23?GHz and 1.78–2.07?GHz with 15% frequency tuning range. Two different inductors are used for the frequency band switching. Frequency tuning is implemented by varying the capacitance of a MOS varactor. The measured phase noise is ?109?dBc/Hz @ 1?MHz and ?112?dBc/Hz @ 1?MHz for frequency at 5.8?GHz and 2?GHz, respectively. This oscillator is fabricated in UMC's 0.18-µm one-poly-six-metal 1.8?V process. The power dissipation of this dual-band VCO is 11.7 and 9.3?mW for oscillation frequency of 2?GHz and 5.8?GHz, respectively.     

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage.     

一种工作在亚阈值区的低电压低功耗基准电压电路

本文提出了一种不使用三极管而只使用工作在亚阈值区的晶体管和电阻的电压基准。使用0.18um工艺进行流片以及测试的结果表明：本文所设计的电压基准可在0.8V的低电压下工作,在温度从-35˚C到85˚C的范围内,温度系数为370ppm/˚C;电源电压从0.8V到3V的条件下,电压偏差小于0.1%。而且在电源电压为0.8V的条件下,整个芯片的功耗只有1.5uA。     

Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED

Edward Lorenz was an early pioneer of the chaos theory. He discovered that small changes in initial conditions produce large changes in long-term outcome, and introduced a chaotic attractor already known as Lorenz chaotic oscillator, which produces a butterfly-like behavior. This and all kinds of continuous-time chaotic oscillators can be simulated with different numerical methods. However, a bad choice of the step size and/or parameters of the mathematical models can produce errors or even mitigate the chaotic behavior. These issues are related to the main property of chaotic oscillators, the high sensitivity to the initial conditions, which is quantified by evaluating the maximum Lyapunov exponent (MLE). The Lorenz and other representative oscillators like Lü, Chua's circuit and Rössler have been implemented using different discrete electronic devices and few ones with integrated circuits (IC) using CMOS technologies. Designing CMOS chaotic oscillators is challenging because a very small variation in their parameters from their mathematical models or in the sizes of the MOS transistors may suppress the chaotic behavior. This article describes how to perform a successful simulation and optimization, and how to synthesize the mathematical models using CMOS technology. The application of metaheuristics to optimize MLE by varying the parameters of the oscillators, and the optimization of the CMOS IC design to guarantee robustness to process, voltage and temperature (PVT) variations, are discussed. Finally, we discuss issues on the application of chaos generators in random number generators, robotics and chaotic secure communication systems.     

一种应用于WIA-PA收发机的低功耗高灵敏度CMOS GFSK解调器

本文针对工业无线传感网WIA-PA标准设计出一款应用于收发机中的低功耗、高灵敏度、频率偏差能够自动消除的GFSK解调器。从低功耗角度出发,该收发机中的接收机采用中频为1.5M的低中频结构,发射机采用基于sigmadelta结构的锁相环间接调制方式。本文提出的GFSK解调器采用TSMC 0.18 um 1P6MRF工艺流片,有效面积为0.14mm2。经测试,该解调器能够处理±180 KHz的频率偏差并没有谐波干扰;在1‰的误码率条件下,仅需要18.5dB的信噪比;并且在1.8V电源供电情况下,整个解调器消耗功耗不超过0.26mA。     

A low-power CMOS analog multiplier

A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.     

PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Increasing in device parameter variations is the critical issue in very deep sub-micron regime due to continue scaling of the transistor dimensions. The overall performance yield of the logic circuit is diminished by raising leakage current and variability issues in scaled devices. In this article; we have proposed an approach called INDEP, based on Boolean logic calculation for the input signals of the extra inserted transistors between the pull-up and pull-down network of the CMOS logic. INDEP approach is not only reduces the leakage current but also mitigates the variability issues with minimum susceptible delay paths. Various process, voltage and temperature (PVT) variations are analyzed at 22 nm BSIM4 bulk CMOS PTM technology node for chain of 5-inverters using HSPICE tool. Several guidelines are provided to design the variability aware CMOS circuits in nanoscale regime by considering the leakage current variation. INDEP approach works effectively in both active as well as standby state of the circuit and keeping the modal performance characteristics of the CMOS gate. The electrical simulation results show that our proposed INDEP approach is less susceptible to PVT variations as compared to conventional circuit. The Monte-Carlo simulation results confirm that average INDEP leakage current reduction is 62.31% at ±20% PVT variations under 3σ Gaussian distribution for chain of 5-inverters.     

A low-power CMOS time-to-digital converter

A time-to-digital converter, TDC, with 780 ps lsb and 10-μs input range has been integrated in a 1.2-μm CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5±0.5 V, and the operating temperature range is -40 to +60°C. Single-shot accuracy is 3 ns and accuracy after averaging is ±120 ps with input time intervals 5-500 ns. In the total input range of 10 μs, the final accuracy after averaging is ±200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm×2.5 mm     

A low-power CMOS analog vector quantizer

We present a parallel analog vector quantizer (VQ) in 2.0-μm double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16×16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic template storage measures 60×78 μm². The output code is produced by a 16-cell winner-take-all (WTA) output circuit of linear complexity which selects the winning template with constant power-decay product, independent of input levels and scale. Experimental results demonstrate 34 dB analog input dynamic range and 0.7 mW power dissipation at 3 μs cycle     

A CMOS low-voltage low-power temperature sensor

Temperature sensing circuits are used in a wide range of applications such as in the biomedical area, cold chain monitoring and industrial applications. In the biomedical area, temperature patient monitoring systems can be found in a wide range of hospital applications such as the intensive care unit, surgery rooms and clinical analysis. When the systems also incorporate also communication features, they form a telemedicine system in which the patients can be remotely monitored. The need of portability promotes a demand for sensors and signal conditioners that can be placed directly on the patient or even implanted. Implanted systems provide comfort for the patient during the physiologic data acquisition. These systems should operate preferably without a battery, in which the energy is obtained by inductive coupling (RF link). Implanted devices require low-voltage and low-power operation in a small silicon area in order to offer safety to the patient, mainly in terms of excessive exposure to RF. This work presents a low-voltage low-power temperature sensor, suitable for implanted devices. The circuit topology is based on the composite transistors operating in weak inversion, requiring extremely low current, at low-voltage (0.8 V), with just 100 nW power dissipation. The circuit is very simple and its implementation requires a small silicon area (0.062 mm²). The tests conducted in the prototypes validate the circuit operation.     

低功耗CMOS限幅放大器设计

利用0.18μm CMOS工艺设计了应用于光接收机中的10Gb/s限幅放大器.此限幅放大器由输入缓冲,4级放大单元,一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路构成.输入动态范围为38dB(10mV～800mV),负载上的输出限幅在400mV,在3.3V电源电压下,功耗仅为99mW.整个芯片面积为0.8×1.3mm2.     

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.     

2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.     

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.     

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications

A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI/sub pp/ at 10 GHz and a phase noise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.     

2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.     

基于电容补偿的高线性低噪声2.4GHz CMOS LC 压控振荡器

实现了一个基于标准0.18µm CMOS工艺的2.4GHz高线性低噪声交叉耦合LC压控振荡器。基于三段分布式偏置的开关容抗管电路和差分开关电容电路,提出了一种调谐灵敏度补偿结构,减小了压控振荡器的增益变化,获得了高线性度和良好的相位噪声性能。与传统结构的压控振荡器相比,本文提出的压控振荡器在整个频率调谐范围内具有更加恒定的增益。当载波频率为2.42GHz 时,在100kHz和1MHz的频偏处相位噪声分别为-100.96dBc/Hz和-122.63dBc/Hz。工作电压为1.8V时,电路功耗为2.5mW。该压控振荡器面积为500×810 µm2。     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².