Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

Process-induced and environmental fluctuations play an important role in the design process for modern high-performance integrated circuits. The conventional principle of considering the verification of worst-case requirements reduces the performance that can potentially be achieved by circuits and technology. This paper presents a new mechanism that permits the compensation of random independent delay fluctuations due to environmental factors. It shows that it is significantly possible to reduce the latency time of a circuit even for a moderate length of pipeline stages.     

Annealing of oxide fixed charges in scaled polysilicon gate MOS structures

Annealing of oxide fixed charges (QF) under polysilicon gate in scaled MOS structures was studied. Our results indicate that, even for a gate width as small as 1.25 µm, QFunderneath the polysilicon gate is unaffected by further processing steps, including high-temperature oxidizing ambients. In other words, the QFtriangle reduces to a horizontal line, even for scaled down polysilicon gate MOS devices. This result has important practical implications, because poly-Si gate is the dominating MOS technology today. A two-dimensional oxygen diffusion model is proposed to explain this phenomenon. Numerical solution was carried out based on the finite difference method. It will be shown that the polysilicon gate not only acts as a barrier to oxygen above the gate oxide, it also keeps oxygen away from the SiO_{2}- Si-substrate interface under the gate edges, thus very effectively shielding the gate oxide from the ambient.     

Dimensional control of sub-half-micron polysilicon gate structures at DUV exposure

Results of dimensional control of sub-half-micron polysilicon gates which pass over LOCOS egdes are presented. Calculations, at duv exposure, using a chemically amplified resist, with and without top and bottom anti-reflective coatings, are performed using SOLID. Results are presented in terms of “swing curves” so that a range of dimensions may be predicted for any linewidth.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Use of the polysilicon gate layer for local interconnect in a CMOStechnology incorporating LDD structures

In conventional single-level polysilicon technologies, the polysilicon gate layer can be used as an interconnect layer through buried contacts between polysilicon and one type of junction (usually n ⁺) in the underlying substrate. The formation and characteristics of buried contacts between n⁺ and p⁺ junctions and a single polysilicon gate layer are discussed. In addition, it is shown that the obstacles posed by the inclusion of oxide-sidewall spacers (common in present-day VLSI CMOS technologies) are surmountable with respect to the formation of useful buried contacts and the resultant local interconnect level that they provide     

Control of boron diffusion in polysilicon for constructing overlapping polysilicon gate charge-coupled devices

The diffusion coefficient of boron having values significantly different in silicon and silicon dioxide has been used to control the doping of boron impurity in intrinsic polysilicon deposited over the gate oxide. The method reduces the possibility of doping gate oxide while diffusing boron in polysilicon. Using the method, silicon gate p-MOSFETS and twenty bit photo-sensor, four phase, double overlapping polysilicon gate surface channel charge-coupled devices have been constructed with a transfer efficiency of 0.9990. The measured values of the threshold voltage of MOSFETS are in close agreement with their corresponding calculated values.     

Amorphous silicon active gate for polysilicon TFT

The excessive leakage current of polycrystalline silicon (polysilicon) TFTs, is one of the major impediments to their use in flat panel displays. The authors present new results on the use of amorphous silicon-based active gates to control the leakage current of the polysilicon TFTs. Moreover, the proposed technology, which is the first implementation of an amorphous silicon active gate recess, relies on a standard process and may ease the design rules for the realisation of TFTs     

Identifying defects in deep-submicron CMOS ICs

With safety margins for reliability, test, failure analysis, and design verification shrinking, it would be a shame to give up the I_DDQ technique-and luckily, we may not have to. Steps can be taken to maintain its applicability as we rush deeper into the submicron regime. We will first examine why the I_DDQ test serves several interests, then describe the challenge posed by 0.35-0.07 μm transistor geometries, and finally propose several solutions     

Experimental study and analysis of corner compensation structures for CMOS compatible bulk micromachining using 25 wt% TMAH

In the present work, most common compensation structures (〈1 1 0〉 squares and 〈1 0 0〉 bars) have been used for convex corner compensation with 25 wt% TMAH-water solution at 90±1 °C temperature. Etch flow morphology and self-align properties of the compensating structures have been investigated. For 25 wt% TMAH water solution {3 1 1} plane is found to be responsible for corner undercutting, which is the fast etch plane. Etch-front-attack angle is measured to be 24°. Generalized empirical formulas are also discussed for these compensation structures for TMAH-water solution. 〈1 1 0〉 square structure protects mesa and convex corner and is the most space efficient compared to other compensation structures, but unable to produce perfect convex corner as 〈1 0 0〉 bar type structures. Both the 〈1 0 0〉 bar structures provide perfect convex corners, but 〈1 0 0〉 wide bar structure is more space efficient than the 〈1 0 0〉 thin bar structure. Implications of these compensation structures with realization of accelerometer structure have also been discussed. A modified quad beam accelerometer structure has been realized with these compensation structures using 25 wt% TMAH.     

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.     

Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed     

CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.     

CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.     

Refractory MoSi2and MoSi2/polysilicon bulk CMOS Circuits

Refractory MoSi2and MoSi2/polysilicon have been used to fabricate high-performance 3µm bulk CMOS circuits. Thirty-nine stage ring oscillators, with a fan-in and fan-out of 1, exhibit a switching delay/stage of 1.2 to 1.4ns, and a power-delay product of 0.22 to 0.25pJ at a supply voltage of 5V. The power-delay product ranges from 40fJ for a delay of 9ns to 1pJ for a delay of 0.6ns. Self-checking pattern generator circuits implemented with the same technology show an operating frequency as high as 80 MHz, which corresponds to approximate in-circuit delays of 1.2ns/stage.     

Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two-pi blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed     

Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs

A compact ladder-shaped electrostatic discharge (ESD) protection circuit is presented for millimetre-wave integrated circuits (ICs) in CMOS technology. Multiple shorted shunt stubs form a ladder network together with series stubs as ESD protection that discharges current/voltage pulses caused by an ESD event, while at the same time the network is embedded as part of the matching circuit for a normal operation. A 60 GHz low-noise amplifier using a 90 nm CMOS process is demonstrated with the proposed ESD protection methodology that introduces less than 1 dB insertion loss. Owing to the ESD current distribution through multiple shorted stubs, the proposed methodology is useful to millimetre-wave ICs with advanced CMOS technology that suffers from higher sheet resistance of the metal layers.     

一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

ESD protection strategies in advanced CMOS SOI ICs

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-micron CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharge (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) requirements in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces a response surface method (RSM) to optimize device sizes in the ESD networks.     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.