高温退火对铸造多晶硅片中位错密度的影响

对铸造多晶硅片进行了1 000~1 400℃的高温退火和不同方式冷却实验,用显微观察法对退火硅片及其相邻姊妹片位错密度进行了测量统计。研究了退火温度和冷却方式对铸造多晶硅片中位错密度的影响。结果证实:当退火温度在1 100℃及以下时,硅片的位错密度并没有降低反而增加了;当退火温度在1 320℃及以上时,硅片的位错密度明显降低,其幅度随温度提高增大;但退火后如断电随炉冷却而不控制冷却速率,位错密度又会提高。     

多晶硅定向凝固工艺中石墨加热器的影响

石墨加热器作为多晶硅铸锭工艺中的热源,它的尺寸和位置直接影响了多晶硅晶体生长过程中的温度分布和固液界面。通过对顶加热器、侧加热器以及顶-侧加热器三种不同的加热器的热场模拟研究,计算结果表明：目前采用的顶-侧加热器在多晶硅熔融和晶体生长过程中能够获得较好的效率和固液界面。     

多晶硅锭定向凝固过程的数值模拟

研究了多晶硅锭定向凝固过程中晶体和熔体中的温度分布、固液界面的温度场,并对定向凝固过程进行了数值模拟,对热场对多晶硅晶体生长的影响进行了系统的理论分析和试验验证。     

多晶硅片表面缺陷的研究与定向凝固多晶硅锭热场模拟

结合实际工艺模拟多晶硅铸锭生产过程中的热场分布情况,研究了该热场对所生产多晶硅片缺陷分布的影响。同时采用对多晶硅片化学腐蚀抛光处理和位错刻蚀液处理之后的表面缺陷形貌表征的方法,以及观察扫描电镜(SEM)视角下其表面微结构,研究了采用定向凝固多晶硅锭工艺所得的多晶硅片表面缺陷情况。结果显示模拟该生产过程中热场分布情况对多晶硅片缺陷的影响和实验所得的结果相吻合。     

用微波等离子体化学气相沉积法低温生长织构多晶硅薄膜

本文报道用微波等离子体沉积／原子氢处理交互进行方法低温制备多晶硅（ｐｏｌｙ－Ｓｉ）薄膜及其结构特征和光电特性．Ｘ光衍射（ＸＲＤ）、透射电镜（ＴＥＭ）、光吸收、光电导等测量分析表明，柱状晶粒分布致密，呈现良好的（２２０）择优取向生长．锐利的光吸收边意味着样品中有很低的带尾态密度，光吸收过程主要由晶粒中电子的带间跃迁所支配．小的光电导激活能说明晶界缺陷密度低，晶界势垒小．所有这些都是由于在薄膜生长过程中引入了氢等离子体的周期性原位处理，不仅抑制了非晶态相的形成、促进了晶粒的生长及织构构造的形成     

太阳能电池多晶硅铸锭的凝固原理和方法浅谈

首先从定向凝固的原理讲起,其中涉及定向凝固的一些重要的工艺参数以及多晶硅铸锭的组织结构;其次,介绍了多晶硅铸锭的几种凝固方法,尤其着重讲了一下热交换法的应用;并在结尾提到了现在铸锭法中需要改进和解决的主要问题。     

多晶硅铸锭炉中准单晶硅锭的生长

介于多晶硅和单晶硅之间的准单晶生长技术逐渐被人们所重视。通过分析单晶硅晶体生长和多晶硅晶体生长的特点,在自主研发的多晶硅铸锭的基础上,介绍了如何通过设备改进和工艺改进,生长出晶体结构优于多晶硅的准单晶。准单晶制作的电池片光伏转换效率显著高于多晶硅。     

定向凝固法制备高转换效率晶体硅专利综述

定向凝固法制备高转换效率晶体硅,其制造成本低、产品的光转换效率高。本文首次综述了定向凝固法制备高转换效率晶体硅制备工艺方面的基础专利发明的技术演进。从定向凝固法的成核、杂质、缺陷、均匀性等多个方面出发,总结了从上述方面出发制备高转换效率硅晶体的专利申请的状况,归纳了有关制备工艺方面的发明点。     

太阳能多晶硅的制备生产工艺研究

太阳能行业使用的多晶硅来源于石英或硅石,经过熔融处理,可获得冶金级金属硅,再经精制成太阳能级多晶硅。太阳能级多晶硅是一种非常关键的材料,处于光伏行业的上游,具有投资大、技术路线复杂等特点。文章以天然形成的硅酸盐制备太阳能级多晶硅的工艺路线为主导,阐述目前国内外太阳能多晶硅的生产技术状况以及各个工艺流程的详细情况。     

GT Solar宣布推出用于采用直接氯化法的多晶硅工厂的新一代氢化炉该公司还面向定向凝固炉客户推出新的生产力合作服务计划

日前在上海举办的国际太阳能光伏大会暨（上海）展览会（SNEC）上宣布面向采用直接氯化法实现四氯化硅氢化的多晶硅生产厂推出其新一代氢化炉。     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ～1/h 模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至 5×10⁶cm^-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在 5×10⁵cm^-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。     

Reduction of Dislocation Density by Producing Novel Structures

HgCdTe, because of its narrow band gap and low dark current, is the infrared detector material of choice for several military and commercial applications. CdZnTe is the substrate of choice for HgCdTe as it can be lattice matched, resulting in low-defect-density epitaxy. Being often small and not circular, layers grown on CdZnTe are difficult to process in standard semiconductor equipment. Furthermore, CdZnTe can often be very expensive. Alternate inexpensive large circular substrates, such as silicon or gallium arsenide, are needed to scale HgCdTe detector production. Growth of HgCdTe on these alternate substrates has its own difficulty, namely large lattice mismatch (19% for Si and 14% for GaAs). This large mismatch results in high defect density and reduced detector performance. In this paper we discuss ways to reduce the effects of dislocations by gettering these defects to the edge of a reticulated structure. These reticulated surfaces enable stress-free regions for dislocations to glide to. In this work, a novel structure was developed that allows for etch pit density of less than 4?×?10⁵/cm² for HgCdTe-on-Si. This is almost two orders of magnitude less than the as-grown etch pit density of 1.1?×?10⁷/cm². This value of 3.35?×?10⁵/cm² is below the <1?×?10⁶/cm² or even the better <5?×?10⁵/cm² target for this research, making HgCdTe-on- alternate substrate density much more like that of HgCdTe-on-CdZnTe.     

Phosphorus Removal from Silicon by Vacuum Refining and Directional Solidification

Silicon is widely used as a raw material for production of solar cells. As a major impurity in silicon, phosphorus must be removed to 1 × 10^?5 wt.%. In the present study, based on the distribution of phosphorus in a silicon ingot obtained by vacuum refining and directional solidification, the mechanism for removal of phosphorus from silicon is investigated. The results show that the distribution is controlled not only by segregation at the solid–liquid interface but also by evaporation at the gas–liquid interface, showing some deviation from Scheil’s equation. A modified model which considers both segregation and evaporation is used to simulate the distribution, matching quite well with the experimental results. The temperature and solidification rate are two important parameters that affect the overall mass transfer coefficient and the effective segregation coefficient and thus the distribution of phosphorus. A high removal efficiency and a homogeneous distribution can be obtained by adjusting these two parameters.     

ZnCdTe衬底上HgCdTe分子束外延的位错密度

报道了用 MBE的方法 ,在 Zn Cd Te衬底上制备 Hg Cd Te薄膜的位错密度研究结果。研究发现Hg Cd Te材料的位错密度与 Zn Cd Te衬底的表面晶体损伤、Hg Cd Te生长条件以及材料组分密切相关。通过衬底制备以及生长条件的优化 ,在 Zn Cd Te衬底上生长的长波 Hg Cd Te材料 EPD平均值达到 4.2× 1 0 5cm- 2 ,标准差为 3 .5× 1 0 5cm- 2 ,接近 Zn Cd Te衬底的位错极限。可重复性良好 ,材料位错合格率为 73 .7%。可以满足高性能Hg Cd Te焦平面探测器对材料位错密度的要求     

应用改进的热场生长低位错SI-CaAs单晶

报道在国产JW一0002型高压单晶炉内设计了一种改进的LEC热场装置,改善了加热区的温度分布,使炉内覆盖剂B_2O_3的轴向温度梯度减少到30～60℃/cm,拉制的φ50mm,<100>晶向的SI—GaAs单晶,其位错密度低于5×10~3cm~(-2),局部无位错。     

Reduction of Dislocation Density in HgCdTe on Si by Producing Highly Reticulated Structures

HgCdTe, because of its narrow band gap and low dark current, is the infrared detector material of choice for several military and commercial applications. CdZnTe is the substrate of choice for HgCdTe as it can be lattice matched, resulting in low-defect-density epitaxy. Being often small and not circular, layers grown on CdZnTe are difficult to process in standard semiconductor equipment. Furthermore, CdZnTe can often be very expensive. Alternative inexpensive large circular substrates, such as silicon or gallium arsenide, are needed to scale production of HgCdTe detectors. Growth of HgCdTe on these alternative substrates has its own difficulty, namely a large lattice mismatch (19% for Si and 14% for GaAs). This large mismatch results in high defect density and reduced detector performance. In this paper we discuss ways to reduce the effects of dislocations by gettering these defects to the edge of a reticulated structure. These reticulated surfaces enable stress-free regions for dislocations to glide to. In the work described herein, HgCdTe-on-Si diodes have been produced with R ₀ A ₀ of over 400 Ω cm² at 78 K and cutoff of 10.1 μm. Further, these diodes have good uniformity at 78 K at both 9.3 μm and 10.14 μm.     

低剂量SIMOX圆片表层硅缺陷密度

用增强化学腐蚀法研究了低剂量 SIMOX- SOI材料表层硅质量与实验参数的关系 .结果表明 ,注入剂量和能量对表层硅质量有明显影响 .通过对注入剂量和能量的优化 ,表层硅线缺陷密度可低于 10 4cm- 2 .在注入能量为16 0 ke V时 ,获得低线缺陷密度对应的注入剂量为 5 .5× 10 1 7cm- 2 左右 ,当注入剂量为 4.5× 10 1 7cm- 2 ,获得低线缺陷密度对应的注入能量为 130 ke V     

低剂量SIMOX圆片表层硅缺陷密度

用增强化学腐蚀法研究了低剂量SIMOX-SOI材料表层硅质量与实验参数的关系.结果表明,注入剂量和能量对表层硅质量有明显影响.通过对注入剂量和能量的优化,表层硅线缺陷密度可低于104cm-2.在注入能量为160keV时,获得低线缺陷密度对应的注入剂量为5.5×1017cm-2左右,当注入剂量为4.5×1017cm-2,获得低线缺陷密度对应的注入能量为130keV.