Ionizing radiation effects on electrical and reliability characteristics of sputtered Ta2O5/Si interface

This paper describes the effect of ionizing radiation on the interface properties of Al/Ta₂O₅/Si metal oxide semiconductor (MOS) capacitors using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The devices were irradiated with X-rays at different doses ranging from 100?rad to 1?Mrad. The leakage behavior, which is an important parameter for memory applications of Al/Ta₂O₅/Si MOS capacitors, along with interface properties such as effective oxide charges and interface trap density with and without irradiation has been investigated. Lower accumulation capacitance and shift in flat band voltage toward negative value were observed in annealed devices after exposure to radiation. The increase in interfacial oxide layer thickness after irradiation was confirmed by Rutherford Back Scattering measurement. The effect of post-deposition annealing on the electrical behavior of Ta₂O₅ MOS capacitors was also investigated. Improved electrical and interface properties were obtained for samples deposited in N₂ ambient. The density of interface trap states (D_it) at Ta₂O₅/Si interface sputtered in pure argon ambient was higher compared to samples reactively sputtered in nitrogen-containing plasma. Our results show that reactive sputtering in nitrogen-containing plasma is a promising approach to improve the radiation hardness of Ta₂O₅/Si MOS devices.     

Asymmetric electrical properties in Pt/Ba0.5Sr0.5Ti0.99Co0.01O3/Nb-doped SrTiO3 capacitors

Ba_0.5Sr_0.5Ti_0.99Co_0.01O₃ (BSTC) thin films have been fabricated with pulsed laser deposition on Nb-doped SrTiO₃ (STN) substrate. In Pt/BSTC/STN capacitor, we systematically investigated the capacitance, leakage current and polarization versus bias voltage characteristics, and found that curves of capacitance versus voltage and leakage current versus voltage were not symmetric, and polarization hysteresis loop exhibited large relaxation of the remnant polarization at negatively poled state. A detailed analysis of capacitance data demonstrated a difference of the built-in voltage between top Pt/BSTC interface (V_b,t=2.5 V) and bottom BSTC/STN interface (V_b,b=1.1 V). Such different built-in voltages lead to the presence of an internal electric field, which results in asymmetric electric characteristics in Pt/BSTC/STN capacitor.     

Effect of annealing temperature on the electrical properties of Au/Ta2O5/n-GaN metal–insulator–semiconductor (MIS) structure

We report on the effect of an annealing temperature on the electrical properties of Au/Ta₂O₅/n-GaN metal–insulator–semiconductor (MIS) structure by current–voltage (I–V) and capacitance–voltage (C–V) measurements. The measured Schottky barrier height (Φ _bo) and ideality factor n values of the as-deposited Au/Ta₂O₅/n-GaN MIS structure are 0.93 eV (I–V) and 1.19. The barrier height (BH) increases to 1.03 eV and ideality factor decreases to 1.13 upon annealing at 500 ^°C for 1 min under nitrogen ambient. When the contact is annealed at 600 ^°C, the barrier height decreases and the ideality factor increases to 0.99 eV and 1.15. The barrier heights obtained from the C–V measurements are higher than those obtained from I–V measurements, and this indicates the existence of spatial inhomogeneity at the interface. Cheung’s functions are also used to calculate the barrier height (Φ _bo), ideality factor (n), and series resistance (R _s ) of the Au/Ta₂O₅/n-GaN MIS structure. Investigations reveal that the Schottky emission is the dominant mechanism and the Poole–Frenkel emission occurs only in the high voltage region. The energy distribution of interface states is determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height. It is observed that the density value of interface states for the annealed samples with interfacial layer is lower than that of the density value of interface states of the as-deposited sample.     

Electrical characteristics of polycrystalline Si layers embedded into high-k Al2O3 gate layers

The electrical characteristics of polycrystalline Si (poly Si) layers embedded into high-k Al₂O₃ (alumina) gate layers are investigated in this work. The capacitance versus voltage (C-V) curves obtained from the metal-alumina-polysilicon-alumina-silicon (MASAS) capacitors exhibit significant threshold voltage shifts, and the width of their hysteresis window is dependent on the range of the voltage sweep. The counterclockwise hysteresis observed in the C-V curves indicates that electrons originating from the p-type Si substrate in the inversion condition are trapped in the floating gate layer consisting of the poly Si layer present between the top and bottom Al₂O₃ layers in the MASAS capacitor. Also, current versus voltage (I-V) measurements are performed to examine the electrical characteristics of the fabricated capacitors. The I-V measurements reveal that our MASAS capacitors show a very low leakage current density, compared to the previously reported results.     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.     

Electrical properties and conduction mechanism of an organic-modified Au/NiPc/n-InP Schottky barrier diode

The effect of nickel phthalocyanine (NiPc) organic interlayer on the electronic parameters of Au/n-InP Schottky contacts has been investigated using current–voltage (I–V) and capacitance–voltage (C–V) measurements. Measurements showed that the barrier heights and ideality factors are 0.58 eV (I–V), 0.69 eV(C–V) and 1.32 for Au/n-InP Schottky contact and 0.80 eV (I–V), 1.12 eV (C–V) and 1.73 for Au/NiPc/n-InP Schottky contact, respectively. Experimental results show that the interfacial layer of NiPc increases the effective barrier height by the influence of the space charge region of the Au/n-InP Schottky junction. Further, Cheung’s and modified Norde functions are used to extract the barrier height, series resistance and ideality factors. The discrepancy between barrier heights estimated from I–V to C–V methods is also explained. Moreover, the energy distribution of interface state density is determined from the forward bias I–V data. Results show that the interface states and series resistance play an important role on electrical properties of the structures studied. The reverse leakage current conduction mechanism is investigated. Results reveal that the Schottky conduction mechanism is found to be dominant in the Au/n-InP Schottky contact. However, in the case of Au/NiPc/n-InP Schottky contact, the Schottky conduction mechanism is found to be dominant in the higher bias region, while Poole–Frenkel conduction is found to be dominant in the lower bias region.     

Memory characteristics of platinum nanoparticle-embedded MOS capacitors

The capacitance characteristics of platinum nanoparticle (NP)-embedded metal–oxide–semiconductor (MOS) capacitors with gate Al₂O₃ layers are studied in this work. The capacitance versus voltage (C–V) curves obtained for a representative MOS capacitor exhibit flat-band voltage shifts, demonstrating the presence of charge storages in the platinum NPs. The counterclockwise hysteresis and flat-band voltage shift, observed from the C–V curves imply that electrons are stored in a floating gate layer consisting of the platinum NPs present between the tunneling and control oxide layers in the MOS capacitor and that these stored electrons originate from the Si substrate. Moreover, the charge remains versus time curve for the platinum NP-embedded MOS capacitor is investigated in this work.     

Al2O3绝缘层的AlGaN/GaN MOSHEMT器件研究

在研制AlGaN/GaN HEMT器件的基础上,采用ALD法制备了Al₂O₃ AlGaN/GaN MOSHEMT器件.通过X射线光电子能谱测试表明在AlGaN/GaN异质结材料上成功淀积了Al₂O₃薄膜.根据对HEMT和MOSHEMT器件肖特基电容、器件输出以及转移特性的测试进行分析发现：所制备的Al₂O₃薄膜与AlGaN外延层间界面态密度较小,因而MOSHEMT器件呈现出较 关键词： 2O₃')" href="#">Al₂O₃ ALD GaN MOSHEMT     

Effects of DC and AC stress on the VT shift of AlGaN/GaN MIS-HEMTs

AlGaN/GaN MIS-HEMTs with adjusted V_T were fabricated using a recess gate to investigate the effect on actual operation when the polarity of the gate voltage is opposite in the on- and off-state. The direction and time exponents of V_T shift depend on the polarity of the gate bias stress. Electrons detrapping from the Al₂O₃/AlGaN interface trap site to AlGaN under negative gate bias stress has to overcome the energy barrier, resulting in a higher temperature dependence. In addition, the unaffected g_m and SS show that the degradation occurred primarily at the Al₂O₃/AlGaN interface rather than channel or mobility degradation. For unipolar and bipolar AC stresses, the time exponent of the V_T shift during stress time has two values, and a relatively low value during relaxation after bipolar AC stress. These results may be due to the further degradation by V_min at the broader energy levels of the Al₂O₃/AlGaN interface.     

Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

Structural characterization of Mg substituted on A/B sites in $$\hbox {NiFe}_2\hbox {O}_4$$ nanoparticles using autocombustion method

A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al_0.25Ga_0.75N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance–voltage (CV) characteristics. Similarly, the predicted threshold voltage (V _T) is analysed by varying barrier thickness and oxide thickness. The positive V _T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model.     

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal–oxide–semiconductor capacitor

In this study, GaAs metal–oxide–semiconductor (MOS) capacitors using Y‐incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 × 10¹¹ cm^–2 eV^–1), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 × 10^–5A/cm² at V_fb + 1 V). These merits should be attributed to the complementary properties of Y₂O₃ and Ta₂O₅:Y can effectively passivate the large amount of oxygen vacancies in Ta₂O₅, while the positively‐charged oxygen vacancies in Ta₂O₅ are capable of neutralizing the effects of the negative oxide charges in Y₂O₃. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices.

Capacitance–voltage characteristic of the GaAs MOS capacitor with TaYON gate dielectric (Y content = 27.6%) proposed in this work with the cross sectional structure and dielectric surface morphology as insets.     

Room-temperature flexible thin film transistor with high mobility

We report a room-temperature and high-mobility InGaZnO thin-film transistor on flexible substrate. To gain both high gate capacitance and low leakage current, we adopt stacked dielectric of Y₂O₃/TiO₂/Y₂O₃. This flexible IGZO TFT shows a low threshold voltage of 0.45 V, a small sub-threshold swing of 0.16 V/decade and very high field-effect mobility of 40 cm²/V. Such good performance is mainly contributed by improved gate stack structure and thickness modulation of IGZO channel that reduce the interface trap density without apparent mobility degradation.     

Current instabilities in dynamic random access memory storage capacitor formed with electron beam deposited Y2O3 dielectric

Metal-oxide-semiconductor (MOS) storage capacitors based on electron beam deposited Y₂O₃ extrinsic dielectric on Si show changes in capacitance density depending on the amorphous and crystalline phases. Bias stress cycle-dependent changes in capacitance density occur due to the non-equilibrium nature of defect states at the Y₂O₃/Si interface after O₂ annealing as a result of the emergence of a 4–8 nm thick SiO₂ film at the interface. Leakage currents show instability under repeated dc bias stress, the nature and extent of which depend upon the structure of the Y₂O₃ gate dielectric and the polarity of dc bias. With amorphous Y₂O₃, leakage currents drift to lower values under gate injection due to electron trapping, and to higher values under Si-injection due to the generation of holes. Though leakage current drift is minimal for crystalline Y₂O₃, its magnitude increases as the energy of injected electrons from mid-gap states is low and the local field due to asperity is high. The emergence of interfacial SiO₂ reduces the magnitude of Si-injection leakage current substantially, but causes transient changes resulting in switching to higher values at a threshold dc bias. Thermal detrapping of holes and reverse bias stress studies confirm that the instability of current is caused by an increase in the cathodic field from hole trapping at interface states. Leakage current instability limits the application of extrinsic high dielectric constant dielectrics in a high density DRAM storage capacitor, unless a new interface layer scheme other than SiO₂ and a method to form a defect-free dielectric layer can be implemented. Received: 29 October 2001 / Accepted: 22 April 2002 / Published online: 4 December 2002 RID="*" ID="*"Corresponding author. Fax: +1-413/545-4611, E-mail: rastogi@ecs.umass.edu     

Stress-induced leakage currents of the RF sputtered Ta2O5 on N-implanted silicon

The electrical (C-V and I-V) and reliability (constant current stress technique) properties of RF sputtered 30 nm thick Ta₂O₅ on N-implanted Si have been investigated. The dependence on the parameters of both Ta₂O₅ and the implanted interfacial layers on the stress time are discussed. The leakage current characteristics are analyzed by previously proposed comprehensive model. It is established that the reliability of the Ta₂O₅-based capacitors can be effectively improved if the Si substrate is a subject to preliminary N-implantation—markedly smaller stress induced leakage current as compared to the films on bare Si are detected. The stress mainly affects the properties of the interfacial layer and the generation of neutral traps is identified to be the primary cause for the stress-induced degradation. It is concluded that the implantation results in a strengthening of the interfacial layer against stress degradation.     

Characterization of Y2O3 gate dielectric on n-GaAs substrates

Physical and electrical properties of sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate are investigated. The as-deposited films and interfacial layer formation have been analyzed by using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). It is found that directly deposited Y₂O₃ on n-GaAs exhibits excellent electrical properties with low frequency dispersion (<5%), hysteresis voltage (0.24 V), and interface trap density (3 × 10¹² eV⁻¹ cm⁻²). The results show that the deposition of Y₂O₃ on n-GaAs can be an effective way to improve the interface quality by the suppression on native oxides formation, especially arsenic oxide which causes Fermi level pinning at high-k/GaAs interface. The Al/Y₂O₃/n-GaAs stack with an equivalent oxide thickness (EOT) of 2.1 nm shows a leakage current density of 3.6 × 10⁻⁶ A cm⁻² at a V_FB of 1 V. While the low-field leakage current conduction mechanism has been found to be dominated by the Schottky emission, Poole-Frenkel emission takes over at high electric fields. The energy band alignment of Y₂O₃ films on n-GaAs substrate is extracted from detailed XPS measurements. The valence and conduction band offsets at Y₂O₃/n-GaAs interfaces are found to be 2.14 and 2.21 eV, respectively.     

Effect of SrTiO3 thickness on the capacitance–voltage characteristics of (La,Sr)CoO3/(Pb,La)(Zr,Ti)O3/SrTiO3/LaVO3 epitaxial heterostructures

We report the effect of SrTiO₃ thickness on the capacitance?Cvoltage (C?CV) characteristics of (La,Sr)CoO₃/(Pb,La)(Zr,Ti)O₃/SrTiO₃/LaVO₃ metal?Cferroelectric?Cinsulator?Csemiconductor (MFIS) epitaxial heterostructures. The C?CV measurement of the heterostructure exhibited the asymmetry of capacitance with respect to gate bias. Within the given thickness range (5?C30 nm), the amount of capacitance reduction at positive gate bias and the rapidness of capacitance reduction decreased with increasing SrTiO₃ thickness, which is consistent with the C?CV characteristics of conventional silicon-based MFIS capacitors. These results suggest that quantitative understanding on the electrical behavior of oxide heterostructures is possible with C?CV analysis, with potentially important implications on their device applications.     

Improved electrical and interfacial properties of RF-sputtered HfAlOx on n-GaAs with effective Si passivation

In this paper, we present the effects of ultrathin Si interfacial layer on the physical and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered HfAlO_x gate dielectric. It is found that HfAlO_x/Si/n-GaAs stack exhibits excellent electrical properties with low frequency dispersion (∼4.8%), hysteresis voltage (0.27 V) and interface trap density (1.3 × 10¹² eV⁻¹ cm⁻²). The current density of 3.7 × 10⁻⁵ A/cm² is achieved with an equivalent-oxide-thickness of 1.8 nm at V_FB + 1 V for Si-passivated HfAlO_x films on n-GaAs. X-ray photoelectron spectroscopy (XPS) analysis shows that the suppression of low-k interfacial layer formation is accomplished with the introduction of ultrathin Si interface control layer (ICL). Thus the introduction of thin layer of Si between HfAlO_x dielectrics and GaAs substrate is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current. Additionally, current conduction mechanism has been studied and the dominant conduction mechanisms are found to be Schottky emission at low to medium electric fields and Poole-Frenkel at high fields and high temperatures under substrate injection. In case of gate injection, the main current conduction at low field is found to be the Schottky emission at high temperatures.     

Physical and electrical characteristics of a high-k Yb2O3 gate dielectric

High-k ytterbium oxide (Yb₂O₃) gate dielectrics were deposited on Si substrate by reactive sputtering. The structural features of these films after postdeposition annealing treatment were studied by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that the Yb₂O₃ gate dielectrics annealed at 700 °C exhibit a larger capacitance value, a lower frequency dispersion and a smaller hysteresis voltage in C-V curves compared with other annealing temperatures. They also show negligible charge trapping under high constant voltage stress. This phenomenon is mainly attributed to the decrease in the amorphous silica thickness.     

Improved Performance of Organic Thin Film Transistor with an Inorganic Oxide/Polymer Double-Layer Insulator

We employ the Ta2Os/PVP （poly-4-vinylphenol） double-layer gate insulator to improve the performance of pentacene thin-film transistors. It is found that the double-layer insulator has low leakage current, smooth surface and considerably high capacitance. Compared to Ta205 insulator layers, the device with the Ta2Os/PVP doublelayer insulator exhibits an enhancement of the field-effect mobility from 0.21 to 0.54 cm2/Vs, and the decreasing threshold voltage from 4.38 V to -2.5 V. The results suggest that the Ta2Os/PVP double-layer insulator is a potential gate insulator for fabricating OTFTs with good electrical performance.