Transport characteristics of a single-layer graphene field-effect transistor grown on 4H-silicon carbide

We have investigated transport characteristics of epitaxial graphene grown on semi-insulating silicon-face 4H-silicon carbide (SiC) substrate by thermal decomposition method in relatively high N₂ pressure atmosphere. We have succeeded in forming 1–2 layers of graphene on SiC in controlled manner. The surface morphology of formed graphene was analyzed by atomic force microscopy (AFM), low-energy electron diffraction (LEED) and low-energy electron microscope (LEEM). We have confirmed single-layer graphene growth in average by this method. Top-gated, single-layer graphene field-effect transistors (FETs) were fabricated on epitaxial graphene grown on 4H-SiC. Increased on/off ratio of nearly 100 at low temperature and extremely small minimum conductance (0.018–0.3 in 4 e²/h) in gated Hall-bar samples suggest possible band-gap opening of single-layer epitaxial graphene grown on Si-face SiC.     

Application of amorphous silicon field effect transistors in integrated circuits

The work described in this paper is concerned with the possible applications in integrated circuits of thin-film field effect transistors (FETs) made from glow discharge amorphous (a-) silicon and silicon nitride. The construction and performance of inverter circuits, employing integrated a-Si load resistors, are described in some detail. The extension of this basic circuit to NAND and NOR gates, to a bistable multivibrator and to a shift register is reported. Based on the excellent photoconductive properties of a-Si an integrated addressable photosensing element has been constructed, which could have potential applications in imaging arrays.     

Small-signal modeling of graphene barristors

This paper presents a small-signal model for graphene barristor, a promising device for the future nanoelectronics industry. Because of the functional similarities to the conventional FET transistors, the same configuration and parameters, as those of FETs, are assumed for the model. Transconductance, output resistance, and parasitic capacitances are the main parameters of the small signal equivalent circuit modeled in this work. Recognizing the importance of physical modeling of novel semiconductor devices, we develop physical compact expressions for the device radio-frequency characteristics. Furthermore, we clarify the physics behind the variation of the characteristics as the device parameters change. We also validate our model results with available simulation results. Impact of equilibrium Schottky barrier height of the graphene–silicon junction on the radio frequency performance of barristor is investigated, too.     

Field-effect transistors based on two-dimensional materials for logic applications

Field-effect transistors （FETs） for logic applications, graphene and MoS2, are discussed. These materials have based on two representative two-dimensional （2D） materials, drastically different properties and require different consider- ations. The unique band structure of graphene necessitates engineering of the Dirac point, including the opening of the bandgap, the doping and the interface, before the graphene can be used in logic applications. On the other hand, MoS2 is a semiconductor, and its electron transport depends heavily on the surface properties, the number of layers, and the carrier density. Finally, we discuss the prospects for the future developments in 2D material transistors.     

Self-connected horizontal silicon nanowire field effect transistor

We propose a technique to fabricate self-connected horizontal Si nanowire (NW) field effect transistors (FETs) by a self-assembly mechanism. We show direct growth of Si NWs between two predefined metallic electrodes along the SiO₂ gate oxide using the vapour–liquid–solid (VLS) growth mode. In our approach, the gold catalyst layer is covered by the contact metal, giving rise to selective and localized catalytic activity and growth of NWs from the gold edges. The diameter of the NWs can be adjusted by the thickness of the catalyst layer. Using such a process, we demonstrate field effect operation on the conductivity of a non-intentionally doped 20 nm diameter Si NW. This technique can be implemented in three dimensions, paving the way to three-dimensionalD integration using vertical stacks of self-connected FETs.     

Performance of ring oscillators composed of gate-all-around FETs with varying numbers of nanowire channels using TCAD simulation

In this paper, we investigate the performance of ring oscillators composed of gate-all-around (GAA) silicon nanowire (NW) field-effect transistors (FETs) with four different numbers of NW channels, for sub-10-nm logic applications. Our simulations reveal that ring oscillators with double, triple, and quadruple NW channels exhibit improvements of up to 50%, 85%, and 97%, respectively, in the oscillation frequencies (f_osc), compared to a ring oscillator with a single NW channel, due to the large drive current, in spite of the increased intrinsic capacitance of a given device. Moreover, our work shows that the f_osc improvement ratio of the ring oscillators becomes saturated with triple NW channels with additional load capacitances of 0.1 fF and 0.01 fF, which are similar to, or less than the intrinsic device capacitance (∼0.1 fF). Thus, our study provides an insight for determining the capacitive load and optimal number of NW channels, for device development and circuit design of GAA NW FETs.     

Simple Analog Complementary Metal Oxide Semiconductor Circuit for Generating Motion Signal

We proposed in this study a novel analog complementary metal oxide semiconductor (CMOS) circuit for generating a motion signal when an object moves, which is a simple structure. The proposed unit circuit was constructed using a previously proposed edge detection circuit and a novel proposed circuit for generating a motion signal which accepts an edge signal. The part for generating the motion signal was constructed using six metal oxide semiconductor (MOS) transistors and one capacitor. Results obtained by the simulation program with integrated circuit emphasis (SPICE) and the measured results of a test circuit constructed with discrete MOS transistors and the test circuit fabricated with a 1.2 μm CMOS process showed that the proposed unit circuit can output pulsed current (motion signal) when an object moves on the circuit. It was clarified from the SPICE results that the two-dimensional network constructed with proposed unit circuits can output motion signals. The size of the novel unit circuit is expected to be about 110 × 110μm² obtained by the 1.2 μm CMOS process. It is possible to arrange 90 × 90 unit circuits on a chip which has an area of 1 × 1cm². The aperture ratio is expected to be about 21%, which is twice as large as that of the previously proposed circuit. An integrated circuit for image processing in real time can thus be realized by applying the two-dimensional network constructed with the proposed circuits.     

Design of Novel Coplanar Counter Circuit in Quantum Dot Cellular Automata Technology

One of the emerging technology that can be used for replacing CMOS technology is Quantum-dot Cellular Automata (QCA) technology. Counter circuits are widely used circuits in the design of digital circuits. This paper presents and evaluates circuits for 2-, 3-, 4-, and 5-bit coplanar counter in the QCA technology. The designed QCA coplanar counter circuits are based on the modified D-Flip-Flop (D-FF) circuit that is designed in this paper. The designed QCA circuits are implemented and verified by using QCADesigner tool version 2.0.3. The results show that the designed circuits for 2-, 3-, 4-, and 5-bit coplanar counter contain 44 (0.03 μm²), 93 (0.07 μm²), 160 (0.13 μm²), and 245 (0.2 μm²) quantum cells (area). The comparison results indicate that the designed circuits have advantages compared to other QCA circuits in terms of cost, area, and cell count.

     

基于毫米级单晶石墨烯的倍频器性能研究

石墨烯作为一种拥有高电子迁移率和高饱和速度的二维材料,在射频电子学领域具有很大的应用潜力,引起了人们广泛的研究兴趣.近些年随着化学气相沉积制备石墨烯技术的发展,高质量大尺寸的单晶石墨烯生长技术也愈加成熟.本文基于化学气相沉积生长的毫米级单晶石墨烯,在高介电常数介质上制备出高性能的石墨烯倍频器,并且对其倍频特性做了系统的研究.研究结果表明:在输入信号频率为1 GHz时,倍频增益可以达到-23.4 dB,频谱纯度可以达到94%.研究了不同漏极偏压以及输入信号功率下倍频增益的变化特性,随着漏极偏压以及输入信号功率的增加,倍频增益增加.对具有不同跨导和电子空穴电导对称性的器件的倍频增益和频谱纯度随输入信号频率f_(in)的变化关系进行了研究.结果表明,跨导对于倍频增益影响显著,在f_(in)=1 GHz时器件的频谱纯度差别不大,均大于90%,但是随着f_(in)增加至4 GHz,电子空穴电导对称性较差的器件频谱纯度下降至42%,电子空穴电导对称性较好的器件仍能保持85%的频谱纯度.这是电子空穴电导对称性和电子空穴响应速度共同作用的结果.本文的研究结果对于高性能石墨烯倍频器设计具有一定的指导意义.     

Interphase microstress measurements in IN 718 by cold neutron diffraction

The linear energy–momentum relation results in more high-energy electrons in 2D (two-dimensional) graphene FETs (field-effect transistor) than those in silicon FETs that features parabolic energy–momentum relation if the same surface electron density has been assumed in all FETs. The numerical calculations demonstrate that, under such assumption, the gate leakage currents in graphene FETs are much larger than that in silicon FETs. The results illustrate that if the conduction band offset between graphene and gate oxide is lower than 3.55 eV, the gate leakage currents in graphene electronics are more significant than those in the silicon electronics.     

Improved charge transport and trap-state distribution in donor–acceptor-type semiconducting copolymer with a fluoropolymer dielectric film

This study presents a p-type doping method for donor–acceptor-type conjugated semiconducting copolymer-based field-effect transistors (FETs) with a fluoropolymer dielectric film. The polymeric FET, which initially comprises a non-polar polymer dielectric layer (poly (methyl methacrylate), PMMA), shows ambipolar behavior owing to the well-balanced electron-accepting and -donating properties of the cyclopentadithiophene (CDT) and pyridyl-2,1,3-thiadiazole (PTz)-based conjugated polymer backbone system. However, when combined with an amorphous fluoropolymer (CYTOP) dielectric layer, the FET device exhibits that their ambipolar behavior remarkably changes to a high-performance p-type FET; the hole mobility enhanced by a factor of ~3 and the threshold voltage significantly shifted from −29 V to −12 V. The density of trap states in the CDT-PTz-based polymeric FETs with a CYTOP dielectric layer, which was estimated from the temperature-dependent transfer characteristics, was narrower and shallower than that of polymeric FETs with a PMMA dielectric layer. As such, it can be inferred that the deep-trap states are filled with additional doped charges from the surface polarization induced by the fluorinated dielectrics at the semiconductor-dielectric interface.     

Comparing the weak and strong gate‐coupling regimes for nanotube and graphene transistors

We present an experimental and theoretical comparison of the weak and strong gate‐coupling regimes that arise for carbon nanotube (CNT) and graphene field‐effect transistors (FETs) in back‐gated and liquid‐gated configuration, respectively. We find that whereas the back‐gate efficiency is suppressed for a liquid‐gated CNT FET, the back gate is still effective in case of a liquid‐gated graphene FET. We calculate the gate‐induced Fermi‐level shifts and induced charge densities. In both strong and weak coupling regimes, nonlinearities occur in the gate dependence of these parameters, which can significantly influence the electronic transport. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Room-temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors

Sub-10 nm wide graphene nanoribbon field-effect transistors (GNRFETs) are studied systematically. All sub-10 nm GNRs afforded semiconducting FETs without exception, with Ion/Ioff ratio up to 10(6) and on-state current density as high as approximately 2000 microA/microm. We estimated carrier mobility approximately 200 cm2/V s and scattering mean free path approximately 10 nm in sub-10 nm GNRs. Scattering mechanisms by edges, acoustic phonon, and defects are discussed. The sub-10 nm GNRFETs are comparable to small diameter (d< or = approximately 1.2 nm) carbon nanotube FETs with Pd contacts in on-state current density and Ion/Ioff ratio, but have the advantage of producing all-semiconducting devices.     

Effect of electrical contact on performance of WSe2 field effect transistors

Two-dimensional (2D) transition metal dichalcogenides (TMDCs) such as tungsten diselenide (WSe₂) have spead many interesting physical properties, which may become ideal candidates to develop new generation electronic and optoelectronic devices. In order to reveal essential features of 2D TMDCs, it is necessary to fabricate high-quality devices with reliable electrical contact. We systematically analyze the effect of graphene and metal contacts on performance of multi-layered WSe₂ field effect transistors (FETs). The temperature-dependent transport characteristics of both devices are tested. Only graphene-contacted WSe₂ FETs are observed with the metal-insulator transition phenomenon which mainly attributes to the ultra-clean contact interface and lowered contact barrier. Further characterization on contact barrier demonstrates that graphene contact enables lower contact barrier with WSe₂ than metal contact, since the Fermi level of graphene can be modulated by the gate bias to match the Fermi level of the channel material. We also analyze the carrier mobility of both devices under different temperatures, revealing that graphene contact can reduce the charge scattering of the device caused by ionized impurities and phonon vibrations in low and room temperature regions, respectively. This work is expected to provide reference for fabricating 2D material devices with decent performances.     

Simple analog edge detection circuit based on vertebrate retina

Novel analog edge detection circuits were proposed and fabricated based on the vertebrate retina. The proposed unit circuit is constructed with one photodiode and about eight n-channel metal oxide semiconductor (MOS) transistors. The results with the simulation program with integrated circuit emphasis (SPICE) showed that the one- and two-dimensional array of proposed circuits can detect edge positions with a dynamic range of about 5 decades. The test circuit was fabricated on the breadboard using discrete MOS transistors. The measured results of the test circuit showed that the proposed circuit can detect edge positions. Under the condition that the photodiode used as the input part of the proposed unit circuit is 4,275 μm², the fill factor of the novel circuit is expected to be about 51.7%. The advanced integrated circuit for edge detection which is characterized by a high fill factor, wide dynamic range and low power consumption can be realized by applying the proposed circuit.     

Analysis of graphene based optically transparent patch antenna for terahertz communications

With and without multi walled carbon nanotube (MWCNT) loaded graphene based optically transparent patch antennas are designed to resonate at 6 THz. Their radiation characteristics are analyzed in 5.66–6.43 THz band. The optically transparent graphene is deployed as the patch and ground plane of the antennas, which are separated by a 2.5 μm thick flexible polyimide substrate. By shorting the microstrip line and ground plane of the antenna with a MWCNT via, the return loss of the antenna is improved. The peak gain of 3.3dB at 6.2 THz and a gain greater than 3dB in 5.66–6.43 THz band is obtained for antenna loaded without MWCNT. Both the antennas achieved a −10dB impedance bandwidth of 12.83%. Gain, directivity and radiation efficiency of the proposed antennas are compared with conventional transparent patch antennas and graphene based non-transparent antennas. The antenna structures are simulated by using finite element method based electromagnetic simulator-Ansys HFSS.     

Millimeter-wave imaging using FET detectors integrated with printed circuit antennas

The application of field effect transistor (FET) detectors integrated with planar twin dipole microstrip antennas to millimeter-wave imaging has been demonstrated. Circuits were configured as practical heterodyne mixers, as elements in a 2×3 element planar focal plane array for imaging, and as receivers in frequency modulated (FM) radars for three-dimensional imaging, at 63 GHz. These experiments show that quasioptical circuits, using conventional present-day FETs and simple printed circuit construction, can be applied usefully in the millimeter-wave region.     

Low noise broadband modulated preamplifiers for a variety of transducers

Often, increases in signal-to-noise ratio and basic sensitivity are gained by the use of carrier modulation. Further advantage can be taken of this process by the use of varactors. These are suitably biased solid-state diodes and transistors, usually used to provide capacitance reactances. Their capacitance is changed by applying a voltage. The change in capacitance available by applying to their terminals the electrical output of a transducer—such as many of the sensors for light, heat, sound, mechanical stress and deformation—can be used in suitable modulating circuits. The magnitudes of reactance available from varactors fall conveniently into the range of values suitable for the carrier frequencies now accessible by means of another stable, mass produced solid-state device, the crystal clock oscillator.In general, the complexity of the carrier circuit to be chosen depends upon the sensitivity and noise floor requirements. This paper describes circuits for applying the modulation process, and discusses the hierarchy of choices for the methods used. The authors have built circuits with an input noise level equivalent to 0·3 μV for signals over the entire audiofrequency range, having a gain in excess of 50 dB.     

Low capacitance ESD protection circuits for GaAs RF ICs

We present a novel electrostatic discharge (ESD) protection circuit for GaAs radio frequency (RF) integrated circuits (ICs), which are targeted for 10 Gb/s fiber-optic communication applications. The robustness, parasitic impedance, and loading effect of the new ESD protection circuit are studied and compared with the conventional diode-based ESD protection technique. Two versions of this type of ESD protection circuit were fabricated with a 60-GHz InGaP heterojunction bipolar transistor (HBT) technology. These two circuits can withstand, respectively, 2700 and 5000 V human body model (HBM) ESD stress and provide a similar level of ESD protection to RF ICs. The corresponding impedances of the off state are represented by an equivalent shunt capacitance and shunt resistance of 0.22 pF and 500 Ω, and 0.5 pF and 250 Ω, at 10 GHz. This ESD protection circuit can protect the 10 Gb/s RF ICs against much higher level ESD stress than conventional diode-based ESD protection circuits even with smaller size.