高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

“聚龙一号”装置磁驱动准等熵压缩实验的一维磁流体力学模拟

国内首台多路并联超高功率脉冲装置"聚龙一号"(PTS)已被用于磁驱动准等熵实验研究,其分时分组放电特点为开展材料的动高压可控路径加载研究提供了便利.磁驱动准等熵实验的物理设计和结果分析需要依赖可靠的数值模拟平台.本文介绍了含强度计算的一维磁流体力学程序MADE1D的物理模型和程序特点,讨论了"聚龙一号"装置两种不同电流波形驱动条件下准等熵实验的模拟情况.结果显示,MADE1D程序能够较好地反映电磁力引起的压缩波在样品内部的产生、传播及发展过程,计算获得的"样品/窗口"界面速度同实验测量结果符合较好.分析发现,电流波形是影响加载过程的重要因素.对于目前使用的带状电极,电流上升率不宜超过40 k A/ns,否则可能在厚度1.2 mm以上的铝样品中产生冲击.     

应变Si NMOSFET漏电流解析模型

基于应变Si/SiGe器件结构,本文建立了统一的应变Si NMOSFET漏电流解析模型. 该模型采用平滑函数,实现了应变Si NMOSFET漏电流及其导数,从亚阈值区到强反型区以及从线性区到饱和区的平滑性,解决了模型的连续性问题. 同时考虑了载流子速度饱和效应和沟道长度调制效应的影响,进一步提高了模型精度. 通过将模型的仿真结果和实验结果对比分析,验证了所建模型的有效性. 该模型可为应变Si数字集成电路和模拟集成电路分析、设计提供重要参考. 关键词： 应变Si NMOSFET 漏电流 解析模型     

材料二次电子产额对腔体双边二次电子倍增的影响

采用蒙特卡罗抽样与粒子模拟相结合的方法,数值研究了材料二次电子产额对腔体双边二次电子倍增瞬态演化及饱和特性的影响.研究发现:随着材料二次电子产额的增加,二次电子增长率以及稳态二次电子数目和振幅均呈现增加的趋势,放电电流起振时间逐步缩短,稳态电流幅值以及放电功率平均值和振幅值均呈现逐步增加并趋于饱和的规律,沉积功率波形延时以及脉宽呈现逐步增加并趋于饱和的趋势.粒子模拟给出了高/低二次电子产额情况下的电子相空间分布、电荷密度分布、平均碰撞能量、平均二次电子产额、二次电子数目和放电电流的细致物理图像.模拟结果表明:高二次电子产额材料,饱和时更倾向趋于单边二次电子倍增类型分布;低二次电子产额材料的二次电子倍增饱和特性由空间电荷场的"去群聚"效应和"反场"效应同时决定,而高二次电子产额材料的二次电子倍增饱和特性则主要是由发射面附近的强空间电荷场"反场"效应决定的.     

“闪光二号”加速器HPIB的产生及应用初步结果

主要给出了“闪光二号”加速器高功率离子束(HPIB)产生及应用研究的初步结果.介绍了强箍缩反射离子束二极管的结构及工作原理，给出了考虑阴阳极产生的等离子体运动对二极管间隙影响的饱和顺位流修正公式.实验得到的离子束峰值能量约500keV，峰值电流约160kA.介绍了利用高功率离子束(质子束)轰击¹⁹F靶产生6—7MeV准单能脉冲γ射线的初步实验结果，给出了利用高功率脉冲离子束模拟1keV黑体辐射x射线对材料的热-力学效应初步研究结果. 关键词： 高功率离子束 箍缩二极管 准单能脉冲γ射线 热-力学效应     

高k栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷,建立了高k栅介质小尺寸绝缘体上锗(Ge OI)p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型.模型包括了速度饱和效应、迁移率调制效应和沟长调制效应,同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响.在饱和区和非饱和区,漏源电流模拟结果与实验数据符合得较好,证实了模型的正确性和实用性.利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响,对Ge OI PMOSFET的设计具有一定的指导作用.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

背栅效应对SOI横向高压器件击穿特性的影响

提出一种SOI基背栅体内场降低BG REBULF(back-gate reduced BULk field)耐压技术. 其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压. 借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS (>600V) 击穿特性的影响，在背栅电压为330V时，实现器件击穿电压1020V，较习用结构提高47.83%. 该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路. 关键词： SOI 背栅 体内场降低 LDMOS     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

带窗口磁驱动准等熵压缩实验模拟

在二维磁驱动数值模拟程序MDSC2中增加了LiF材料的材料参数和功能模块,使MDSC2程序具有了求解带窗口磁驱动准等熵压缩实验的能力。采用MDSC2程序,对大电流脉冲功率装置上的exp-3-window、exp-6-window带窗口磁驱动准等熵压缩实验进行了模拟。数值模拟结果表明,二维磁驱动数值模拟程序MDSC2能正确模拟带窗口磁驱动准等熵压缩实验exp-3-window和exp-6-window的全过程,模拟的飞片/窗口界面速度在飞片/窗口界面速度的上升阶段、峰值附近和卸载阶段与实验测量基本一致,验证了新程序的计算有效性。MDSC2程序对带窗口磁驱动准等熵压缩实验的正确模拟有助于磁驱动样品物性实验的研究。     

An equivalent circuit characterization of power MOSFET accounting for high field and high frequency effects

An equivalent circuit model for analyzing the AC characteristics of power VDMOS transistors is presented. The model accounts for high field and saturation effects. This is achieved by incorporating dependent voltage and current sources in the device model. Results are given for the AC characteristics of a POLYFET F2001 Power VDMOSFET rated with a drain current of 1.4A, power out of 2.5W at 1GHz. The linear, quasi-saturation and saturation regions of the IV characteristics are accounted for in the analysis. The small signal device parasitics are extracted through s-parameter methods. The s-parameter results were used to extract the frequency dependent parasitics including parasitic capacitances, inductances and transconductances.     

Fabricating high performance n-channel lateral double diffused metal–oxide–semiconductor transistors utilizing the shallow trench isolation as a salicide blocking mask of the drift region

In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 μm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BV_DSS, over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

An investigation of electron and oxygen ion damage in Si npn RF power transistors

Abstract

The effects of 8 MeV electrons and 60 and 95 MeV oxygen ions on the electrical properties of Si npn RF power transistors have been investigated as a function of fluence. The dc current gain (h _FE), displacement damage factor, excess base current (Δ I _B=I _Bpost?I _Bpre), excess collector current (Δ I _C=I _Cpost?I _Cpre), collector saturation current (I _CS) and deep level transient spectroscopy trap signatures of the irradiated transistors were systematically evaluated.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.     

Effect of Temperature Variation on the Characteristics of Microwave Power AlGaN/GaN MODFET

The prime motivation for developing the proposed model of AlGaN/GaN microwave power device is to demonstrate its inherent ability to operate at much higher temperature. An investigation of temperature model of a 1 μm gate AlGaN/GaN enhancement mode n-type modulation-doped field effect transistor (MODFET) is presented. An analytical temperature model based on modified charge control equations is developed. The proposed model handles higher voltages and show stable operation at higher temperatures. The investigated temperature range is from 100 °K–600 °K. The critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak dc trans-conductance (g_m), and unity current gain cut-off frequency (f_T). The calculated values of f_T (10–70 GHz) at elevated temperature suggest that the operation of the proposed device has sufficiently high current handling capacity. The temperature effect on saturation current, cutoff frequency, and trans-conductance behavior predict the device behavior at elevated temperatures. The analysis and simulation results on the transport characteristics of the MODFET structure is compared with the previously measured experimental data at room temperature. The calculated critical parameters suggest that the proposed device could survive in extreme environments.     

Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

Novel high-voltage power device based on self-adaptive interface charge

This paper presents a novel high-voltage lateral double diffused metal--oxide semiconductor (LDMOS) with self-adaptive interface charge (SAC) layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer (E_I) and increase breakdown voltage (BV). The BV and E_I of SAC LDMOS increase to 612 V and 600 V/μm from 204 V and 90.7 V/μm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of η which present the enhanced ability of interface charge on E_I are defined and analysed.     

The effects of high-energy ion irradiations on the I–V characteristics of silicon NPN transistors

The silicon NPN rf power transistors were irradiated with different linear energy transfer (LET) ions such as 50?MeV Li³⁺, 80?MeV C⁶⁺ and 150?MeV Ag¹²⁺ ions in the dose range of 1–100?Mrad. The SRIM simulation was used to understand the energy loss and range of these ions in the transistor structure. The different electrical parameters such as Gummel characteristics, excess base current (ΔI_B), DC current gain (h_FE), displacement damage factor (K) and output characteristics were systematically studied before and after irradiation. The ion irradiation results were compared with ⁶⁰Co-gamma irradiation result in the same dose range. A considerable increase in base current (I_B) and a decrease in h_FE and I_CSat were observed after irradiation. The degradation in the electrical parameters was comparably very high for Ag¹²⁺ ion-irradiated transistor when compared to other ion-irradiated transistors, whereas the degradation in the electrical parameters for Li³⁺ and C⁶⁺ ion-irradiated transistors was comparable with gamma-irradiated transistor. The isochronal annealing study was conducted on the 100?Mrad irradiated transistors up to 500°C to analyze the recovery in different electrical parameters. The h_FE and other electrical parameters of irradiated transistors were almost recovered after 500°C for 50?MeV Li³⁺, 80?MeV C⁶⁺ ion and ⁶⁰Co-gamma-irradiated transistors, whereas for 150?MeV Ag¹²⁺ ion-irradiated transistor, the recovery in electrical characteristics is not complete.     

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m ^{− 1}on-current and on/off current ratios of 10⁶, for a conservative oxide thickness of 40 Å and | V_g − V_t| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | V_t| is obtained in devices with gate lengths ranging from 100 to 20 nm.