Extended Synchronous Dataflow for Efficient DSP System Prototyping

Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes it unsuitable for multimedia signal processing applications that need global states for efficient implementation. In this paper, we propose synchronous piggybacked dataflow (SPDF), an extension of SDF model to accommodate global states without side effects. Global states are accessed by a special block that piggybacks the global state update request on data samples. Such an extension enlarges the domain of application where dataflow representation can be used for rapid system prototyping. The only penalty it incurs is scheduling complexity since the scheduler now considers control dependency as well as data dependency. We present the static analysis of the SPDF model and an implementation technique for memory efficient code synthesis. Finally, we show experimental results with a real life example, MPEG-audio decoder, to present the novelty and usefulness of our approach.     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations

Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflow-based graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations.We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier for general SDF graphs. We show that our customization to acyclic graphs significantly reduces the complexity of the general PGAN algorithm, and we present a formal study of our modified PGAN technique that rigorously establishes its optimality for a certain class of applications. The second approach that we consider is a top-down technique, based on a generalized minimum-cut operation, that was introduced recently in [14]. We present the results of an extensive experimental investigation on the performance of our modified PGAN technique and the top-down approach and on the trade-offs between them. Based on these results, we conclude that these two techniques complement each other, and thus, they should both be incorporated into SDF-based software implementation environments in which the minimization of memory requirements is important. We have implemented these algorithms in the Ptolemy software environment [5] at UC Berkeley.     

OCDMA系统中一种新的多倍长光垂直码

提出了一种新的容量大、相关性好的多倍长、多波长二维光正交码（2D MW-OOC），基于多倍长一维光正交码（1DOOC）构造了MW-OOC。对同时使用具有2种码长的MW-OOC的光码分多址（OCD-MA）系统性能分析表明，使用该MW-OOC的系统性能良好，明显好于同样码长下的多倍长1-DOOC；使用短码序列的信号误码率性能好于使用长码序列信号的误码率性能。这些特征能充分发挥OCDMA系统大容量的技术优势，满足将来大容量多媒体OcDMA网络系统对同时传输的不同信号所需传输质量不同的需求。     

一种基于低码率LDPC码的编码与导频联合辅助载波同步算法

针对深空通信系统中编码和导频辅助载波同步算法分别存在同步范围与精度受限的问题,该文提出一种基于编码与导频联合辅助的载波同步算法。首先按照最优导频放置方式设计了一种基于相关函数和的粗同步算法,其频率估计量的精度接近CRB界;然后分析了导频结构对算法估计精度与范围的影响机理;接着通过加入导频及频率积分器的方式对基于期望最大的细同步算法进行了改进;最后用码率为1/12的低码率LDPC-Hadamard码对算法进行了仿真验证。结果表明新算法可以大幅提高同步参数的估计范围与精度,在一定的导频长度下能达到理想同步。     

迭代译码的级联Reed-Solomon乘积码与卷积码

该文提出用Reed Solomon(RS)乘积码作为外码,卷积码作为内码的级联码方案并且内外码间用Congruential向量生成的交织图案对RS码符号进行重排列。对此级联码采用的迭代译码基于成员码的软译码算法。当迭代次数达到最大后,通过计算RS码的校正子,提出一种纠正残余错误的方法,进一步提高了系统的误比特性能。仿真结果表明,在AWGN信道中与迭代译码的级联RS/卷积码相比,当误比特率为1e-5时,新系统的编码增益大约有0.4 dB。     

有效书写记忆介质的编码构造方法

本文证明线性码的陪集构成的线性陪集码可以渐近达到有效书写记忆介质的容量，并且说明线性码的覆盖半径是有效书写记忆介质的线性陪集码的一个重要参数。本文同时给出有效书写记忆介质的纠错码的一种构造方法。     

一种高效时钟树综合实现方法

针对ASIC芯片设计中时钟树综合效率和时序收敛的问题,提出了一种高效的时钟树综合方法,特别适用于现代先进深亚微米工艺中的高集成度、高复杂度的设计中。改进了传统时钟树综合方法,通过采用由下至上逐级分步综合的方法实现。该设计方法在SMIC 0.18μm eflash工艺下的一款电力线载波通信芯片中成功流片验证,结果表明分步综合能够在实现传统设计功能的前提下,在完成时序收敛时有效减少不必要的器件插入,从而减小芯片面积,降低整体功耗,有效改善绕线拥塞度。     

An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture

To meet strict speed and power requirements for embedded applications, many high-end digital Signal Processors (DSPs) commonly employ non-orthogonal architectures that are typically characterized by irregular data paths, heterogeneous registers, and multiple memory banks. Obviously to harvest the benefits provided by this non-orthogonal architecture sufficient compiler support is necessary and important. However, the complexity of such architectures presents a great challenge to compiler design and the usual compilation techniques for general-purpose CPUs do not adapt well to the irregularity of DSP. The entire code generation process must include the following phases: intermediate representation, code compaction, instruction scheduling, memory bank assignment (or variable partition), and register/accumulator assignment. Much related research only considers some phases, which is inadequate. In this paper, we present an effective code generation algorithm named Rotation Scheduling with Spill Codes Predicting (RSSP) to maximally exploit the benefits of non-orthogonal architectures. It contains six parts that cover almost the entire phases of the code generation process. As well as introducing the detailed principles and algorithms of the proposed RSSP, we use an analytic model to evaluate its preliminary performance. Evaluation results clearly demonstrate the effectiveness of the proposed method. Furthermore, we also present some preliminary ideas to generalize RSSP, which can make it more practicable and suit various DSPs with similar architectural features.

光正交码构造算法的研究

介绍了代数同余算法和遗传算法在光码分多址系统中的应用,研究了使用这些算法构造光正交码的特性,分析了它们的优缺点.     

基于逐幸存路径处理的空时格形码自适应解码器

本文探讨了无线移动信道中空时格形码的一种自适应解码技术.通过分析无周期间插正交导引信号下空时格形码的最大似然序列检测,指出可利用逐幸存路径处理得到该情形下可实用的最大似然序列检测算法;以此为依据,结合利用自调整LMS算法实现的信道跟踪,本文提出一种空时格形码的自适应解码器,该解码器具有所采用信道跟踪参数与信道衰落速度无关的优点;文章最后给出计算机仿真结果.     

MIMO系统中的分组全分集全码率空时编码

针对未编码的多输入多输出（MIMO，Multi—Input Multi—Output）系统，提出一种复杂度适中的分组全分集全码率（GFDFR，Group—wise Full Diversity Full Rate）空时编码方案。该方案通过在发送端进行天线分组，各组独立编码，减小全分集全码率（FDFR，Full Diversity Full Rate）编码块的大小从而降低系统编解码复杂度；在频率选择性信道中，进一步对子载波分组进行独立编码，获得频率分集（或多径分集），以适中的复杂度在不降低系统分集度的情况下保证了信息的全码率传输，是一种在MIMO信道中极具实用价值的空时编码方案。     

一种应用于实时语音传输的LDPC码的设计

文中设计了一种适于对声码器的输出码流进行前向纠错编码的低密度奇偶校验码(LDPC码).该低密度奇偶校验码具有半规则化的结构,编码简单,存储量少,调整码率方便,易于硬件实现.文中同时对汉明码,卷积码、Turbo码、低密度奇偶校验码分别在AWGN、Rayleigh信道下的传输性能进行了仿真比较.仿真结果表明,长度适合的LDPC码误码性能远超过汉明码、卷积码,综合性能与Turbo码接近.     

DSP环境下C代码的手工汇编优化

由于DSP器件的特殊结构,使得该平台上C编译器的效率较低,编译生成的汇编代码含有大量冗余,无法充分发挥DSP强大的运算能力,因而对C语言程序进行手工汇编优化就成为DSP软件开发和移植中常用的方法。TMS320C5410是TI推出的一款16位定点DSP芯片,结合在该芯片上优化实现G.729语音编码压缩算法的经验,详细探讨了手工汇编优化过程中使用的优化策略以及其他注意事项。     

满速率串行级联空时分组MTCM编码方法研究

该文研究了级联空时编码系统在编码增益,分集增益和传输能量效率的限定下最大化传输速率的问题,提出了一种在保留TCM编码方法校验位冗余的同时,还可获得满速率串行级联空时分组TCM编码方法。新方法通过引入具有不同功率分集因子的正交发射码字矩阵,并给出新的译码算法,从而使得新的编码方法在获得满速率的同时还可以获得满分集增益。分析和MATLAB仿真结果表明,在相同的编码状态数下,新方法在编码增益上比现有的满速率超正交空时分组编码方法提高1dB左右。     

一种新的空时格形码软判决自适应解码算法

本文提出一种针对空时格形码的软判决自适应双向解码算法.通过执行双向解码,该解码算法充分利用了TDMA下行链路相邻时隙的前导序列,并给出高质量的软判决解码输出;同时,所提出的两步最小均方算法以较低的运算开销实现了对时变信道的自适应跟踪.文章最后给出计算机仿真结果.     

面向DVB-S2标准LDPC码的高效编码结构

面向DVB-S2标准LDPC码,该文旨在实现一种基于FPGA的高效编码结构,提出一种快速流水线并向递归编码算法,可以显著提高编码数据信息吞吐率。同时,通过并向移位运算和并向异或运算的处理结构计算编码中间变量及校验位信息,在提高编码并行度的同时可有效减少存储资源的消耗。此外,针对动态自适应编码的情况优化了LDPC码编码存储结构,有效复用了数据存储单元和RAM地址发生器,进一步提高FPGA的硬件逻辑资源利用率。针对DVB-S2标准LDPC码,基于Stratix IV系列FPGA的验证结果表明,所提编码结构在系统时钟为126.17 MHz时,编码数据信息吞吐率达20 Gbps以上。     

格子Boltzmann并行程序的优化与性能分析

基于现代计算机的多级存储结构,采用消息传递并行编程模型对格子Boltzmann并行程序进行了Cache优化.实验结果表明,优化后的程序能够减少80%的Cache缺失,性能提高20%,而且经过预处理的并行程序性能也有很大提高.     

一种新的GPS接收机C/A码跟踪环鉴别器算法

该文分析了GPS C/A码相位估计误差与载波频率估计误差对相关函数的影响,并推导出了相关公式。从线性,对信号幅度与载波频率估计误差的敏感性和计算量等角度分析了现有的码鉴别器算法的优缺点。基于上面的分析与研究,提出了一种新的C/A码鉴别器算法。通过理论分析与仿真实验,证明该算法有良好的线性特性,能有效抑制对信号幅度与载波频率估计误差的敏感性,且计算量低,跟踪精度高,抗多经性能好,在性能上优于已有的算法。     

扩展三值纠一检二码原理与设计

本文在三值汉明码一位检错纠错研究工作的基础上,对三值汉明码的检错纠错方法进行进一步研究.给出了扩展三值汉明码的形式,通过对扩展三值汉明码的错误分析获得了一位纠错和二位检错原理,给出了扩展三值汉明码的纠错码表,根据纠错码表提出了一位纠错方法,给出了基于三值光学计算机的扩展三值汉明码检错纠错概念结构图和功能部件,为检错纠错系统的光学设计提供一种途径.