考虑工艺波动的RC互连树统计功耗

为了有效分析考虑工艺波动的RC互连树统计功耗,本文首先给出了考虑工艺波动的互连寄生参数和输入驱动点导纳矩的构建方法,然后,推导得出了互连功耗均值与标准差的表达式.计算结果表明,与目前广泛应用的Monte Carlo分析方法相比,采用本文方法得到的RC互连功耗均值误差小于4.36 %,标准差误差则小于6.68 %.结果显示,本文方法在确保精度的前提下大大缩短了仿真时间. 关键词： 工艺波动 RC互连')" href="#">RC互连 统计功耗     

A statistical RCL interconnect delay model taking account of process variations

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.     

工艺参数扰动下互连线时延的随机点匹配评估算法

提出了一种基于工艺参数扰动的随机点匹配时延评估算法.该算法通过Cholesky分解将具有强相关性的工艺随机扰动转化为独立随机变量,并结合随机点匹配方法和多项式混沌理论对耦合随机互连线模型进行时延分析.最后,利用数值计算方法给出互连时延的有限维表达式.仿真实验结果表明,该算法与HSPICE仿真时延的相对误差不超过2%,且相比于HSPICE显著降低了电路模拟时间. 关键词： 工艺参数扰动 随机互连模型 随机点匹配方法 多项式混沌理论     

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.     

一种基于延时和带宽约束的纳米级互连线优化模型

基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90 nm,65 nm和45 nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计. 关键词： 纳米互连功耗 缓冲器面积 延时 带宽     

一种考虑硅通孔电阻-电容效应的三维互连线模型

硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.     

考虑温度分布效应的非对称RLC树时钟偏差研究

提出了一种RLC互连树零时钟偏差构建方法.给出了RLC互连温度非均匀分布及其延时的解析公式,并推导计算了最优的零时钟偏差点,所提模型同时考虑了互连温度非均匀分布、电感效应及不对称互连结构对零时钟偏差点的影响.针对65 nm工艺节点对所提模型进行了仿真验证,结果显示,相较于同类模型,最大误差不超过1%. 关键词： RLC')" href="#">RLC 温度分布 不对称互连结构 零时钟偏差点     

延时对色关联噪声诱导的逻辑生长过程的影响

应用小延时近似方法,研究了色关联噪声诱导的延时逻辑生长过程,得到了肿瘤细胞数的稳态概率分布P_st(x)的近似解析表达式,发现延时τ的变化可以使P_st(x)发生由多极值结构向单极值结构的转换,延时τ还可以使随机系统的平均值〈x〉、二阶矩〈x²〉、归一化涨落V_ar的极值位置和极值大小发生改变. 关键词： 逻辑生长过程 延时 关联色噪声 统计性质     

RC电路暂态过程的探究式实验教学

运用探究式实验教学方法，由学生自行设计完成了RC电路的暂态过程实验．实践证明，探究式教学有利于培养学生的创新能力。     

基于MATLAB的RC串联电路暂态过程仿真

对RC串联电路暂态过程进行了研究,并对其进行了理论分析,最后利用MATLAB的绘图功能,对实验现象进行了仿真,仿真结果与实验相符.     

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.     

方波激励下的一阶RC响应的简捷解析

通过简易的数学方法,比较直观地解析描述了RC电路在周期为T、幅值为U m和占空比为δ的方波电压u激励下的电容器C上的响应电压u c的变化情况,得出u c在u的上升沿和下降沿上的值将分别单调连续地收敛于U m(1-A 1)A 2/(1-A 1 A 2)和U m(1-A 1)/(1-A 1 A 2),其中A 1=e-Tδ/(RC)和A 2=e-T(1-δ)/(RC).同时也对各参数之间的关系进行了分析探讨.所得结论不但有助于理解和分析方波激励下的一阶RC暂态过程的实验现象,也有助于改善实验设计时对参数的选择.     

A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS

Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.     

有丢失物缺陷的铜互连线中位寿命的定量研究

本文研究了六层互连线上的丢失物缺陷对互连电迁移中位寿命的影响,提出了各层互连线缺陷处的温度模型和缺陷在不同互连层的中位寿命模型,能够定量地计算缺陷对互连电迁移中位寿命的影响,给出了提高互连线中位寿命的方法.研究结果表明：互连线宽度与缺陷处互连线有效宽度的比值越大,互连线寿命越短;缺陷处的温度越高,互连线寿命越短.在互连线参数变化明显的层与层之间,互连线寿命受比值和温度的双重影响,寿命急剧下降.根据该物理模型可以准确计算出互连线具体的温度和寿命数据,可以直接指导集成电路的设计和工艺制造. 关键词： 丢失物缺陷 中位寿命 可靠性 铜互连     

Demonstration of the centralized optical backplane architecture in a three-board microprocessor-to-memory interconnect system

A prototype of a novel interconnection architecture called the centralized optical backplane (COB) was experimentally demonstrated in a three-board microprocessor-to-memory interconnect system. COB keeps the advantages of bus architecture while at the same time providing uniform optical signal fan-outs. In the prototype, the required connectivity for the microprocessor-to-memory interconnect was achieved by using a COB. The optoelectronic interface modules were optimized to support high-speed processing elements at data rates up to 1.25 Gbps. This demonstration illustrates the conceptual design of the COB and its feasibility in real systems.     

基于双电源电压和双阈值电压的全局互连性能优化

基于双电源电压和双阈值电压技术,提出了一种优化全局互连性能的新方法.文中首先定义了一个包含互连延时、带宽和功耗等因素的品质因子用以描述全局互连特性,然后在给定延时牺牲的前提下,通过最大化品质因子求得优化的双电压数值用以节省功耗.仿真结果显示,在65 nm工艺下,针对5%,10%和20%的允许牺牲延时,所提方法相较于单电压方法可分别获得27.8%,40.3%和56.9%的功耗节省.同时发现,随着工艺进步,功耗节省更加明显.该方法可用于高性能全局互连的优化和设计. 关键词： 全局互连 双电源电压 双阈值电压 功耗     

Configurational Effects in Statistical Theory of Branched Non-Random Polycondensation

The statistical theory of gelation in the simplest process of the non-random polycondensation (S. I. Kuchanov, T. V. Zharnikov, J. Stat. Phys., 111(5/6), 1273 (2003)) has been refined as to be able to take into account the effect of a monomer configuration on topological characteristics of the polymer network of the gel. Proceeding from the kinetic analysis of such a polycondensation, we rigorously prove that it can be described in terms of some stochastic branching process. The parameters of the process depend on the overall number of functional groups in the monomer as well as on the pattern of their mutual arrangement. Examples of some model systems illustrate the effect of kinetic and configurational factors on the topology of a polymer network formed in the course of non-random polycondensation.     

基于VxWorks的PCI设备驱动程序设计

阵列天线控制系统采用实时操作系统VxWorks,为了实现控制系统计算机与单元天线的通信,在控制系统计算机中采用PCI设备与单元天线通信,并且基于VxWorks实时操作系统开发了PCI设备的驱动程序。主要完成了板级支持包的修改、PCI设备的初始化,以及功能函数的设计。经试验验证,该驱动程序工作稳定可靠,可以应用于控制系统中。     

RC并联电路的交流阻抗谱

交流阻抗谱技术在实际研究中具有广泛应用,利用交流阻抗谱分析了单时间常数和双时间常数RC并联电路的频率特性,给出了单时间常数和双时间常数的复平面阻抗谱特点。     

组合利用统计和结构信息的道路提取算法

提出了一种组合利用统计和结构信息从遥感图像中提取道路的算法,这个算法包括三个处理步骤,利用道路的多种局部统计特性获得道路基元与道路段,以及利用能量函数提取道路边沿,在检测道路基元时,用统计分析来表达道路的结构信息,避免了提取线段来表达,增强了抗噪性与稳健性;在检测和拟合道路边沿时,能量函数中的参数由前面的运算结果确定,使算法具有自适应能力。