Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure

The threshold voltage (V_th) of the p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ_1,p, polarization charge density σ_b, and equivalent unite capacitance C_oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_th, and threshold voltage |V_th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V_th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10¹⁶ cm^-3 at V_GS = -12 V and V_DS = -10 V.     

Migration of weakly bonded oxygen atoms in a-IGZO thin films and the positive shift of threshold voltage in TFTs

Amorphous indium-gallium-zinc oxide (a-IGZO) thin films are prepared by pulsed laser deposition and fabricated into thin-film transistor (TFT) devices. In-situ x-ray photoelectron spectroscopy (XPS) illustrates that weakly bonded oxygen (O) atoms exist in a-IGZO thin films deposited at high O₂ pressures, but these can be eliminated by vacuum annealing. The threshold voltage (V_th) of the a-IGZO TFTs is shifted under positive gate bias, and the V_th shift is positively related to the deposition pressure. A temperature variation experiment in the range of 20 K-300 K demonstrates that an activation energy of 144 meV is required for the V_th shift, which is close to the activation energy required for the migration of weakly bonded O atoms in a-IGZO thin films. Accordingly, the V_th shift is attributed to the acceptor-like states induced by the accumulation of weakly bonded O atoms at the a-IGZO/SiO₂ interface under positive gate bias. These results provide an insight into the mechanism responsible for the V_th shift of the a-IGZO TFTs and help in the production of reliable designs.     

Ferroelectric effect and equivalent polarization charge model of PbZr_(0.2)Ti_(0.8)O_3 on AlGaN/GaN MIS-HEMT

PbZr_(0.2)Ti_(0.8)O_3(PZT) gate insulator with the thickness of 30 nm is grown by pulsed laser deposition(PLD) in AlGa N/Ga N metal–insulator–semiconductor high electron mobility transistors(MIS-HEMTs). The ferroelectric effect of PZT Al Ga N/Ga N MIS-HEMT is demonstrated. The polarization charge in PZT varies with different gate voltages. The equivalent polarization charge model(EPCM) is proposed for calculating the polarization charge and the concentration of two-dimensional electron gas(2 DEG). The threshold voltage(Vth) and output current density(IDS) can also be obtained by the EPCM. The theoretical values are in good agreement with the experimental results and the model can provide a guide for the design of the PZT MIS-HEMT. The polarization charges of PZT can be modulated by different gate-voltage stresses and the Vthhas a regulation range of 4.0 V. The polarization charge changes after the stress of gate voltage for several seconds. When the gate voltage is stable or changes at high frequency, the output characteristics and the current collapse of the device remain stable.     

超短沟道绝缘层上硅平面场效应晶体管中热载流子注入应力导致的退化对沟道长度的依赖性

随着场效应晶体管(MOSFET)器件尺寸的进一步缩小和器件新结构的引入, 学术界和工业界对器件中热载流子注入(hot carrier injections, HCI)所引起的可靠性问题日益关注. 本文研究了超短沟道长度(L=30–150 nm)绝缘层上硅(silicon on insulator, SOI)场效应晶体管在HCI应力下的电学性能退化机理. 研究结果表明, 在超短沟道情况下, HCI 应力导致的退化随着沟道长度变小而减轻. 通过研究不同栅长器件的恢复特性可以看出, 该现象是由于随着沟道长度的减小, HCI应力下偏压温度不稳定性效应所占比例变大而导致的. 此外, 本文关于SOI器件中HCI应力导致的退化和器件栅长关系的结果与最近报道的鳍式场效晶体管(FinFET)中的结果相反. 因此, 在超短沟道情况下, SOI平面MOSFET器件有可能具有比FinFET器件更好的HCI可靠性.     

High linearity AlGaN/GaN HEMT with double-Vth coupling for millimeter-wave applications

We demonstrated an AlGaN/GaN high electron mobility transistor(HEMT)namely double-Vthcoupling HEMT(DVC-HEMT)fabricated by connecting different threshold voltage(Vth)values including the slant recess element and planar element in parallel along the gate width with N;O plasma treatment on the gate region.The comparative studies of DVC-HEMT and Fin-like HEMT fabricated on the same wafer show significantly improved linearity of transconductance(Gm)and radio frequency(RF)output signal characteristics in DVC-HEMT.The fabricated device shows the transconductance plateau larger than 7 V,which yields a flattened fT/fmax-gate bias dependence.At the operating frequency of 30 GHz,the peak power-added efficiency(PAE)of 41%accompanied by the power density(Pout)of 5.3 W/mm.Furthermore,the proposed architecture also features an exceptional linearity performance with 1-d B compression point(P1 d B)of 28 d Bm,whereas that of the Fin-like HEMT is 25.2 d Bm.The device demonstrated in this article has great potential to be a new paradigm for millimeter-wave application where high linearity is essential.     

65 nm互补金属氧化物半导体场效应和晶体管总剂量效应及损伤机制

对65 nm互补金属氧化物半导体工艺下不同尺寸的N型和P型金属氧化物半导体场效应晶体管(NMOSFET和PMOSFET)开展了不同偏置条件下电离总剂量辐照实验.结果表明:PMOSFET的电离辐射响应与器件结构和偏置条件均有很强的依赖性,而NMOSFET表现出较强的抗总剂量性能;在累积相同总剂量时,PMOSFET的辐照损伤远大于NMOSFET.结合理论分析和数值模拟给出了PMOSFET的辐射敏感位置及辐射损伤的物理机制.     

Ozone oxidation of 4H-SiC and flat-band voltage stability of SiC MOS capacitors

We investigate the effect of ozone (O₃) oxidation of silicon carbide (SiC) on the flat-band voltage (V_fb) stability of SiC metal-oxide-semiconductor (MOS) capacitors. The SiC MOS capacitors are produced by O₃ oxidation, and their V_fb stability under frequency variation, temperature variation, and bias temperature stress are evaluated. Secondary ion mass spectroscopy (SIMS), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) indicate that O₃ oxidation can adjust the element distribution near SiC/SiO₂ interface, improve SiC/SiO₂ interface morphology, and inhibit the formation of near-interface defects, respectively. In addition, we elaborate the underlying mechanism through which O₃ oxidation improves the V_fb stability of SiC MOS capacitors by using the measurement results and O₃ oxidation kinetics.     

Bias-dependent timing jitter of 1-GHz sinusoidally gated InGaAs/InP avalanche photodiode

We characterized the dependence of the timing jitter of an InGaAs/InP single-photon avalanche diode on the excess bias voltage(V_(ex)) when operated in 1-GHz sinusoidally gated mode.The single-photon avalanche diode was cooled to-30 degrees Celsius.When the V_(ex) is too low(0.2 V-0.8 V) or too high(3 V-4.2 V),the timing jitter is increased with the V_(ex),particularly at high V_(ex).While at middle V_(ex)(1 V-2.8 V),the timing jitter is reduced.Measurements of the timing jitter of the same avalanche diode with pulsed gating show that this effect is likely related to the increase of both the amplitude of the V_(ex) and the width of the gate-on time.For the 1-GHz sinusoidally gated detector,the best jitter of 93 ps is achieved with a photon detection efficiency of 21.4%and a dark count rate of ~2.08×10~(-5) per gate at the V_(ex) of 2.8 V.To evaluate the whole performance of the detector,we calculated the noise equivalent power(NEP) and the afterpulse probability(P_(ap)).It is found that both NEP and P_(ap) increase quickly when the V_(ex) is above 2.8 V.At ~2.8-V V_(ex),the NEP and P_(ap) are ~2.06×10~(16)W/Hz~(1/2) and 7.11%,respectively.Therefore,the detector should be operated with V_(ex) of 2.8 V to exploit the fast time response,low NEP and low P_(ap).     

开态应力下电压和电流对AlGaN/GaN高电子迁移率晶体管的退化作用研究

通过采集等功率的两种不同开态直流应力作用下AlGaN/GaN高电子迁移率晶体管(HEMTs)漏源电流输出特性、源区和漏区大信号寄生电阻、转移特性、阈值电压随应力时间的变化, 并使用光发射显微镜观察器件漏电流情况, 研究了开态应力下电压和电流对AlGaN/GaN高电子迁移率晶体管的退化作用. 结果表明, 低电压大电流应力下器件退化很少, 高电压大电流下器件退化较明显. 高电压是HEMTs退化的主要因素, 栅漏之间高电场引起的逆压电效应对参数的永久性退化起决定性作用. 除此之外, 器件表面损坏部位的显微图像表明低电压大电流下器件失效是由于局部电流密度过高, 出现热斑导致器件损伤引起的.     

嵌入Ag纳米颗粒层的DNA忆阻器

构建了具有“Al/DNA-CTMAB/Ag NPs/DNA-CTMAB/ITO”结构的有机忆阻器件, 并对其电流-电压 (I-V)曲线进行测量. 结果表明, 嵌入Ag纳米颗粒层, 不仅可以增强器件的导电性, 而且忆阻特性也显著提高. 当颗粒粒径在15–20 nm范围时, 开-关电流比I_ON/I_OFF能够达到10³. 器件的I-V特性受扫描电压幅值V_A的影响, 随着V_A的增大, 高阻态的电流变化较小, 而低阻态的电流明显增大, 开(或关)电压V_SET (V_RESET)和I_ON/I_OFF增加. 实验还发现, 器件高低阻状态的相互转换取决于外加电场的方向, 说明该忆阻器具有极性.     

Reveal the large open-circuit voltage deficit of all-inorganicCsPbIBr2 perovskite solar cells

Due to excellent thermal stability and optoelectronic properties, all-inorganic perovskite is one of the promising candidates to solve the thermal decomposition problem of conventional organic—inorganic hybrid perovskite solar cells (PSCs), but the larger voltage loss (V_loss) cannot be ignored, especially CsPbIBr₂, which limits the improvement of efficiency. To reduce V_loss, one promising solution is the modification of the energy level alignment between the perovskite layer and adjacent charge transport layer (CTL), which can facilitate charge extraction and reduce carrier recombination rate at the perovskite/CTL interface. Therefore, the key issues of minimum V_loss and high efficiency of CsPbIBr₂-based PSCs were studied in terms of the perovskite layer thickness, the effects of band offset of the CTL/perovskite layer, the doping concentration of the CTL, and the electrode work function in this study based on device simulations. The open-circuit voltage (V_oc) is increased from 1.37 V to 1.52 V by replacing SnO₂ with ZnO as the electron transport layer (ETL) due to more matching conduction band with the CsPbIBr₂ layer.     

Parametric studies on generation of short CO2 laser pulses for IR-laser chemistry

Results of parametric studies on short CO₂ laser pulse generation by laser induced dielectric breakdown in a plasma shutter cell are described. From the rise time of such short pulses obtained, threshold breakdown intensity (I_th) has been estimated for different gases. The technique is further extended to obtain 40 ns pulses on two-frequency emission from a single TEA CO₂ laser. Pressure dependent studies of I_th are utilised to model the process of such laser induced plasma.     

铌镁酸铅-钛酸铅铁电阴极电子发射特性

研究了铌镁酸铅-钛酸铅铁电材料的铁电、介电性能对阴极发射阈值电压的影响, 以及铁电阴极发射电流与激励脉冲电压和抽取电压之间的关系, 并分析了其发射机理. 结果表明, 室温介电常数高、极化强度变化量大的弛豫铁电体0.9Pb(Mg_1/3Nb_2/3)O₃-0.1PbTiO₃具有较小的发射阈值电压; 铁电阴极电子发射与快极化反转和等离子体的形成有关; 由极化反转所致电子发射的自发射电流随激励脉冲电压的增大呈幂律增长关系, 其发射电流开始于激励脉冲电压的下降沿; 在抽取电压较大时, 发射电流随抽取电压的增大呈线性增长关系, 说明大电流主要取决于抽取电压; 其发射电流开始于激励脉冲电压的上升沿, 与“三介点”处的场增强效应和等离子体的形成有关; 当抽取电压为2500 V 时, 得到的发射电流幅值为210 A, 相应的电流密度为447 A/cm².     

Determination of localized states in porous silicon

We determined the density of state distribution near the Fermi level in porous silicon from the analysis of the current–voltage (J–V) and the current–thickness (J–T) characteristics in the space-charge-limited-current (SCLC) regime. The distribution exhibits a minimum density at the Fermi level, which is similar to the U-shape-trap-distribution observed in crystalline Si–SiO₂ interface or in amorphous Si. Theoretical analysis well explains both the J–V and the J–L characteristics, which implies that the current flow is entirely controlled by localized states situated at the quasi-Fermi level.     

Analysis of frequency-dependent series resistance and interface states of In/SiO2/p-Si (MIS) structures

In this work, the investigation of the interface state density and series resistance from capacitance–voltage (C–V) and conductance–voltage (G/ω−V) characteristics in In/SiO₂/p-Si metal–insulator–semiconductor (MIS) structures with thin interfacial insulator layer have been reported. The thickness of SiO₂ film obtained from the measurement of the oxide capacitance corrected for series resistance in the strong accumulation region is 220 Å. The forward and reverse bias C–V and G/ω−V characteristics of MIS structures have been studied at the frequency range 30 kHz–1 MHz at room temperature. The frequency dispersion in capacitance and conductance can be interpreted in terms of the series resistance (R_s) and interface state density (D_it) values. Both the series resistance R_s and density of interface states D_it are strongly frequency-dependent and decrease with increasing frequency. The distribution profile of R_s–V gives a peak at low frequencies in the depletion region and disappears with increasing frequency. Experimental results show that the interfacial polarization contributes to the improvement of the dielectric properties of In/SiO₂/p-Si MIS structures. The interface state density value of In/SiO₂/p-Si MIS diode calculated at strong accumulation region is 1.11×10¹² eV⁻¹ cm⁻² at 1 MHz. It is found that the calculated value of D_it (≈10¹² eV⁻¹ cm⁻²) is not high enough to pin the Fermi level of the Si substrate disrupting the device operation.     

单晶金刚石氢终端场效应晶体管特性

基于微波等离子体化学气相淀积生长的单晶金刚石制作了栅长为2μm的耗尽型氢终端金刚石场效应晶体管,并对器件特性进行了分析.器件的饱和漏电流在栅压为-6 V时达到了96 mA/mm,但是在-6 V时栅泄漏电流过大.在-3.5 V的安全工作栅压下,饱和漏电流达到了77 mA/mm.在器件的饱和区,宽5.9 V的栅电压范围内,跨导随着栅电压的增加而近线性增大到30 mS/mm.通过对器件导通电阻和电容-电压特性的分析,氢终端单晶金刚石的二维空穴气浓度达到了1.99×10~(13)cm~(-2),并且迁移率和载流子浓度均随着栅压向正偏方向的移动而逐渐增大.分析认为,沟道中高密度的载流子、大的栅电容以及迁移率的逐渐增加是引起跨导在很大的栅压范围内近线性增加的原因.     

量子计算正三角形腔内的氢负离子光剥离截面

用传统量子力学方法研究了横截面为正三角形的腔内氢负离子光剥离, 得到了光剥离截面随能量变化的解析表达公式. 该公式还给出了剥离截面的阈值行为. 进一步研究发现, 当氢负离子处于正三角形一角附近时, 用量子力学方法得到的结果与氢负离子处于60°角域内时使用闭合轨道理论得到的结果一致.     

Development of highly integrated RSFQ circuits on the basis of intrinsically shunted Josephson junctions

At PTB, for application in rapid single flux quantum (RSFQ) and voltage standard circuits, the development of highly integrated SDE circuits is focused on devices based on intrinsically shunted Josephson junctions in the SINIS and SNS technologies. In SINIS technology, the fabrication process has been optimized to values of the critical current density of j_C=500 A/cm² and the characteristic voltage of V_C=190 μV. To raise the circuit integration level, successive steps of development are shown by the example of the layout of an elementary RSFQ cell designed for higher values of j_C. In SNS technology, a fabrication process has been developed to produce small ramp-type junctions with contact areas smaller than 0.4 μm² and with values for j_C and V_C of about j_C=200 kA/cm² and V_C=20 μV. The design allows the SNS junction size to be further reduced down to the deep sub-micron range.     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻