Macromolecular nanoelectronics

We have explored new organic materials and fabrication methods to fabricate organic photodiodes and light emitting diodes. Grafting of a fullerene derivative to a polythiophene backbone yielded an integrated acceptor-donor polymer that we used as the active material in organic photodiodes. Using a method of soft lithography, soft embossing, we fabricated submicron structures to be used as organic light emitting diodes. Employing a silicone rubber replica (stamp) of an optical diffraction grating we transferred the grating pattern to an organic resist layer by placing the stamp in conformal contact with the resist. The transferred pattern was subsequently used as an etch mask for the processing of the device. The structures were successfully utilized as light emitting diodes and photodiodes, with device characteristics influenced by the imposed structure.     

Subsystem fault tolerance with the Bacon-Shor code

We discuss how the presence of gauge subsystems in the Bacon-Shor code [D. Bacon, Phys. Rev. A 73, 012340 (2006)10.1103/PhysRevA.73.012340 (2006)] leads to remarkably simple and efficient methods for fault-tolerant error correction (FTEC). Most notably, FTEC does not require entangled ancillary states, and it can be implemented with nearest-neighbor two-qubit measurements. By using these methods, we prove a lower bound on the quantum accuracy threshold, 1.94 x 10(-4) for adversarial stochastic noise, that improves previous lower bounds by nearly an order of magnitude.     

Electron spectroscopy of objects for nanoelectronics

An electron-spectroscopic analysis is made of layered nanostructures and clusters at the surface and in the bulk of a solid. A new method of forming metal/insulator/semiconductor (superconductor) nanostructures is proposed based on ion-stimulated metal segregation effects at the surface of low-temperature gallium arsenide and a 123 high-temperature superconductor. The geometric parameters and electronic structure of these nano-objects are studied. It is shown that their electronic properties can be controllably varied in situ by acting on the surface. The dimensional transformation of the electronic properties of metal clusters is studied for clusters in the insulator SiO₂, in the superconductor LTMBE-GaAs, and on silicon and graphite surfaces. The nature of this transformation is clarified. A diagnostics for cluster ensembles is developed by which one can determine the parameters needed to describe singleelectron transport: the average number of atoms per cluster, the average distance between clusters and isolated atoms, and the chemical state of the atoms. Ensembles of silver clusters with specified parameters are obtained on a silicon surface. It is shown that these ensembles are potentially useful for developing single-electron devices. Zh. Tekh. Fiz. 69, 85–89 (September 1999)     

Research directions and challenges in nanoelectronics

The search for alternate information processing technologies to sustain Moore's Law improvements beyond those attainable by scaling of charge-based devices encompasses several key technologies. Some of these technologies were explored at the Third Workshop on Silicon Nanoelectronics and Beyond (SNB III) held at the National Science Foundation in Washington DC in December 2005. They included: (1) non-charge-based devices; (2) devices operated out of thermal equilibrium; (3) alternative interconnect systems; (4) thermal extraction limits and technologies; and (5) fabrication via directed self-assembly. Although this paper was inspired by this highly successful workshop, it is not intended as a summary, but rather an assessment by the authors of some of the fundamental physical considerations evident at the present time.     

超导量子计算系统中的容错技术

随着超导系统中的量子控制技术日益成熟,量子纠错技术也在不断发展。最近,已有一些平台实现了超越量子纠错盈亏平衡点的里程碑式突破。然而,要实现最终目标——容错量子计算,仍需要拓展系统的维度并进一步压制噪声。文章以超导量子系统为例,首先介绍了四种实现容错错误症状测量的思路;以此为基础,讨论了实现容错量子计算的三个关键阶段以及各阶段所面临的挑战,包括超越盈亏平衡点、达到容错阈值和实现完备逻辑门操作。为了实现这些目标,将按照连通性从低到高归纳三种可能的拓展系统规模的方案。此外,还总结了实验上纠错技术的进展以及对连通性的探索,最后讨论当前关键的研究问题。     

NEMS/MEMS tools for nanoelectronics development

Present information technologies use semiconductor devices and magnetic/optical discs, however, they are all foreseen to face fundamental limitations within a decade. Therefore, superseding devices are required for the next paradigm of high performance information technologies. This paper describes prospects for single molecule devices suitable for future information processing technologies. Possible four milestones for realizing the Peta (P: 10¹⁵)/Exa (E: 10¹⁸)––floating operations per second (FLOPS) personal molecular supercomputer are proposed. Current status and necessary technologies of the first milestone are described, and necessary technologies for the next three milestones are also discussed.     

Surface passivation technology for III-V semiconductor nanoelectronics

The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors’ group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy (MBE)-grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented.     

一种容差模拟电路的分级故障诊断方法

In this paper, a tolerance analog circuit fault diagnosis method based on hierarchical fault dictionary is proposed. During the simulation before test, firstly, the Worse-Case Analysis is used to get the normal characteristics output interval of the circuit under test and the output interval is saved as the first class fault dictionary, which will be used to fault detection; secondly, node-voltage sensitivity sequence is used as fault characteristics to build the second class fault dictionary for locating fault component; thirdly, based on simulation before test according to dividing the component parameters into seven segments, the third class fault dictionary is built to identify the parameter interval of components. In the fault diagnosis stage, based on the established three-class fault dictionary, fault detection, fault locating and component parameter interval identification can be realized respectively according to practical application. The proposed method can improve the efficiency of diagnosis after test and the solution will be a meaningful reference for practical applications. Finally, the simulation experiment demonstrates the effectiveness of the proposed method.     

Physical modeling of seismic source generation in failure of fault asperities

A series of full-scale experiments was performed to study the influence of impact loads on the parameters of seismic vibrations initiated in variable friction. The study was conducted on a test setup Tribo which is a movable concrete slab modeling an allochthon on a rough plane of the Angara fault segment in Baikal region. Contact interactions of asperities in the slip zone were recorded using strain and load measuring equipment and four seismic stations Baykal-7HR widely used for recording earthquakes. The proposed physical modeling method and obtained results can be of interest for the development of new physical models of differently scaled sources of seismic energy dissipation in tectonic faults and can be useful for seismological studies, related data interpretation, and improvement of extended forecast of rock bursts and earthquakes.     

Plasma-produced ultra-thin platinum-oxide films for nanoelectronics: physical characterization

We present a detailed experimental characterization of ultra-thin platinum-oxide films formed on metallic Pt surfaces using O₂ plasma treatment. A monotonic consumption of the metallic Pt by the O₂ plasma is demonstrated by electrical resistance measurements of micron-wide, ultra-thin metallic Pt wires for the range of O₂ plasma exposure times explored in this study. Conversely, angle-resolved X-ray photoelectron spectroscopy (AR-XPS) of the plasma-treated Pt reveals that the oxide layer formed on the Pt surface maintains a constant thickness over these exposure times. In combination, these data demonstrate that the O₂ plasma treatment of Pt simultaneously forms and etches an ultra-thin platinum-oxide layer on the Pt surface. In addition, the AR-XPS data also reveals the oxide layer to be composed of two different platinum–oxygen compounds. Detailed analysis demonstrates a stratified structure for the ultra-thin platinum oxide, with the oxide bulk being composed of PtO₂, likely with PtO defects, and the exposed oxide surface being Pt(OH)_y2 terminated after exposure to ambient conditions. The potential utility of using plasma oxidization to form ultra-thin platinum (or other metal) oxide films on nanoscale metal structures for nano- and molecular-electronic applications is discussed, along with other promising applications in technologies such as sensors and catalysts. PACS 61.43.Dq; 68.47.Gh; 68.55.Ac; 68.55.Jk; 73.50.Bk; 73.61.At; 73.63.Nm; 79.60.Dp     

Plasmonics – the missing link between nanoelectronics and microphotonics

Plasmonics is an exciting new device technology that has recently emerged. It exploits the unique optical properties of metallic nanostructures to enable routing and manipulation of light at the nanoscale. A tremendous synergy can be attained by integrating plasmonic, electronic, and conventional dielectric photonic devices on the same chip and taking advantage of the strengths of each technology. We will provide a perspective on future directions and possibilities for integrating plasmonic devices on a Si chip. PACS 42.82.-m; 42.82.Ds     

Plasma synthesis of semiconductor nanocrystals for nanoelectronics and luminescence applications

Functional nanocrystals are widely considered as novel building blocks for nanostructured materials and devices. Numerous synthesis approaches have been proposed in the solid, liquid and gas phase. Among the gas phase approaches, low pressure nonthermal plasmas offer some unique and beneficial features. Particles acquire a unipolar charge which reduces or eliminates agglomeration; particles can be electrostatically confined in a reactor based on their charge; strongly exothermic reactions at the particle surface heat particles to temperatures that significantly exceed the gas temperature and facilitate the formation of high quality crystals. This paper discusses two examples for the use of low pressure nonthermal plasmas. The first example is that of a constricted capacitive plasma for the formation of highly monodisperse, cubic-shaped silicon nanocrystals with an average size of 35 nm. The growth process of the particles is discussed. The silicon nanocubes have successfully been used as building blocks for nanoparticle-based transistors. The second example focuses on the synthesis of photoluminescent silicon crystals in the 3–6 nm size range. The synthesis approach described has enabled the synthesis of macroscopic quantities of quantum dots, with mass yields of several mg/hour. Quantum yields for photoluminescence as high as 67% have been achieved.     

Focused-electron-beam-induced processing (FEBIP) for emerging applications in carbon nanoelectronics

Focused-electron-beam-induced processing (FEBIP), a resist-free additive nanomanufacturing technique, is an actively researched method for “direct-write” processing of a wide range of structural and functional nanomaterials, with high degree of spatial and time-domain control. This article attempts to critically assess the FEBIP capabilities and unique value proposition in the context of processing of electronics materials, with a particular emphasis on emerging carbon (i.e., based on graphene and carbon nanotubes) devices and interconnect structures. One of the major hurdles in advancing the carbon-based electronic materials and device fabrication is a disjoint nature of various processing steps involved in making a functional device from the precursor graphene/CNT materials. Not only this multi-step sequence severely limits the throughput and increases the cost, but also dramatically reduces the processing reproducibility and negatively impacts the quality because of possible between-the-step contamination, especially for impurity-susceptible materials such as graphene. The FEBIP provides a unique opportunity to address many challenges of carbon nanoelectronics, especially when it is employed as part of an integrated processing environment based on multiple “beams” of energetic particles, including electrons, photons, and molecules. This avenue is promising from the applications’ prospective, as such a multi-functional (electron/photon/molecule beam) enables one to define shapes (patterning), form structures (deposition/etching), and modify (cleaning/doping/annealing) properties with locally resolved control on nanoscale using the same tool without ever changing the processing environment. It thus will have a direct positive impact on enhancing functionality, improving quality and reducing fabrication costs for electronic devices, based on both conventional CMOS and emerging carbon (CNT/graphene) materials.     

Preparation,properties, and applications of laser-prepared intercalated structures in nanoelectronics

Experimental investigation of the structure and electrical properties of layered gallium selenide and indium selenide crystals laser-intercalated by copper and gallium is discussed.     

Analysis and modeling of resistive switching mechanism oriented to fault tolerance of resistive memory based on memristor

With the progress of the semiconductor industry, resistive memories, especially the memristor, have drawn increasing attention. The resistive memory based on memrsitor has not been commercialized mainly because of data error. Currently, there are more studies focused on fault tolerance of resistive memory. This paper studies the resistive switching mechanism which may have time-varying characteristics. Resistive switching mechanism is analyzed and its respective circuit model is established based on the memristor Spice model.     

Interface models and processing technologies for surface passivation and interface control in III-V semiconductor nanoelectronics

Interface models and processing technologies are reviewed for successful establishment of surface passivation, interface control and MIS gate stack formation in III-V nanoelectronics. First, basic considerations on successful surface passivation and interface control are given, including review of interface models for the band alignment at interfaces, and effects of interface states in nanoscale devices. Then, a brief review is given on currently available surface passivation technologies for III-V materials, including the Si interface control layer (ICL)-based passivation scheme by the authors’ group. The Si-ICL technique has been successfully applied to surface passivation of nanowires and to formation of a HfO₂ high-k dielectric/GaAs interfaces with low values of the interface state density.     

Twin fault interactions

We present a calculation of twin fault interactions in the simple metals. The results indicate that the interaction is quite short-range; being negligible beyond four interplanar spacings.