单片集成MEMS中的阳极键合工艺

分析了阳极键合工艺的原理及其工艺条件对CMOS电路的影响，并通过理论分析和实验研究了单片集成MEMS中的两种阳极键合方法：对于玻璃在硅片上方的键合方式，通过在电路部分上方玻璃上腐蚀一定深度的腔及用氮化硅层保护电路可以在很大程度上减轻阳极键合工艺的影响；而玻璃在硅片下方的键合方式，硅片上的电路几乎不受阳极键合工艺的影响，两种方法各有优缺点。     

低温阳极键合工艺研究

对低温阳极键合特性进行了研究.通过对硅片进行亲水、疏水和表面未处理3 种不同处理方式研究其对键合的影响,键合前将硅片浸入去离子水（DIW）中不同时间,研究硅表面H基和氧化硅分子数量对键合的影响.结果表明经亲水处理的硅片在水中浸泡1 h 的键合效果最佳.并设计了不同烘烤时间下的阳极键合实验,表明在100 °C 下烘烤30 min 可以有效减少气泡的数量和尺寸.由不同工艺条件下得到的键合形貌可知,通过控制硅片表面微观状态可以达到减小或消除键合气泡的目的.     

晶圆混合键合工艺优化研究

随着集成电路制造工艺技术的发展和不断进步,一种永久性晶圆键合技术可以在不需要光刻尺寸的进一步缩小而增加IC制造的复杂性的情况下使芯片平面尺寸大幅减小,今天已成为热门的研究方向.而且该晶圆键合工艺可以将图像传感器感光芯片与专用集成电路芯片连接起来,大幅降低信号衰减,从而提升产品性能.但是,在晶圆键合过程中,通常会发生键合...     

基于阳极键合的硅微圆盘多环谐振陀螺的设计与制作

提出了一种新型的基于阳极键合的硅微圆盘多环谐振陀螺的结构设计及其制作方法.该种陀螺采用MEMS工艺制作而成,基底材料为肖特BF33玻璃,电极和谐振器均由单晶硅片加工而成,肖特BF33玻璃与单晶硅片通过阳极键合工艺键合在一起.介绍了该种陀螺的基本结构、工作原理,并进行了仿真分析,得出该种陀螺具有较小的频率分裂,表现出陀螺效应.最后,通过MEMS工艺进行了实际加工,得到了该种陀螺的实验样品.     

超声辅助对PEO-LiClO4与Al阳极键合质量的影响

聚氧化乙烯-高氯酸锂(PEO-LiClO4)与Al的阳极键合工艺中,因键合温度较高,容易引起两者热膨胀系数不匹配、产生残余应力问题.针对这些问题,利用自主搭建的超声辅助阳极键合系统进行工艺实验,通过设计阳极键合与超声辅助键合的对比实验,进而分析键合电流和键合强度的变化趋势,从而验证超声辅助阳极键合工艺的可行性.研究结果...     

基于聚合物介质的低温硅硅键合研究

聚合物低温键合技术是MEMS器件圆片级封装的一项关键技术。以苯并环丁烯(BCB)、聚对二甲苯(Parylene)、聚酰亚胺(Polyimide)、有机玻璃(PMMA)作为键合介质,对键合的温度、压力、气氛、强度等工艺参数进行了研究,并分析了其优缺点。通过改变Parylene的旋涂、键合温度、键合压力、键合时间等工艺参数进行了优化实验。结果表明,在230 ℃的低温键合条件下封装后的MEMS器件具有良好的键合强度(＞3.600 MPa),可满足MEMS器件圆片级封装要求。     

高级IC封装中新兴的细铜丝键合工艺

在铜丝或铜条长期应用于分立器件及大功率器件的同时,近年又出现了晶片的铜金属化工艺。由此,业内人士采用铜作为丝焊键合的一种材料,进而带来了一些新工艺的研究。结果证实,铜金属化使电路的线条更细、密度晚高。因而铜丝可以作为一种最有发展前景及成本最低的互连材料替换金丝,进行大量高引出端数及小焊区器件的球形或楔形键合工艺。本文要阐述了铜丝键合工艺在IC封装中的发展现状及未来发展方向。     

等离子清洗技术在键合工艺中的应用

本文介绍了等离子清洗工艺所依据的原理和技术，通过对瓣膜混合集成电路的实验说明了它应用于键合工艺前的必要性和实用性，指出等离子清洗工艺是提高产品可靠性的一种有效手段。     

用于MEMS器件的键合工艺研究进展

随着MEMS器件的广泛研究和快速进步,非硅基材料被广泛用于MEMS器件中.键合技术成为MEMS器件制作、组装和封装的关键性技术之一,它不仅可以降低工艺的复杂性,而且使许多新技术和新应用在MEMS器件中得以实现.目前主要的键合技术包括直接键合、阳极键合、粘结剂键合和共晶键合.     

MEMS圆片级真空封装金硅键合工艺研究

提出一种适用于微机电系统(MEMS)圆片级真空封装的键合结构,通过比较分析各种键合工艺的优缺点后,选择符合本试验要求的金硅键合工艺.根据所提出键合结构和金硅键合的特点设计键合工艺流程,在多次试验后优化工艺条件.在此工艺条件下,选用三组不同结构参数完成键合试验.之后对比不同的结构参数分别测试其键合质量(包括键合腔体泄漏率...     

High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding

We demonstrate layer transfer of 150 nm of Si from a 200-mm, silicon-on-insulator (SOI) substrate onto a sapphire substrate using low-temperature wafer bonding (T=150°C). The crystalline quality and the thermal stability of the transferred Si layer were characterized by x-ray diffraction (XRD). A broadening of the (004) Si peak is observed only for anneal temperatures T_A≥800°C, indicating some degradation of the crystalline quality of the transferred Si film above these temperatures. The measured electron Hall mobility in the bonded Si layer is comparable to bulk silicon for T_A≤800°C, indicating excellent material quality.     

采用界面薄层氧化硅的硅片直接键合技术研究

本文研究了采用界面薄层氧化硅的硅片直接键合技术。利用原子力显微镜（AFM）和剪切力测试分别表征表面粗糙度和键合强度随着薄层氧化硅厚度的变化情况。对比了采用热氧化和等离子体增强化学气相沉积法（PECVD）两种方法对晶片粗糙度及键合强度的影响。结果表明采用热氧化和PECVD沉积薄层氧化硅做硅片直接键合,键合强度分别可以达到18MPa和8MPa,键合强度随着薄层界面氧化硅厚度的增加而下降,这对于MEMS器件制备及其他硅片直接键合的应用都具有十分重要的指导意义。     

Germanium-on-insulator substrates by wafer bonding

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogen-implanted Ge substrate to a thermally oxidized, silicon handle wafer, are studied for properties relevant to device fabrication. The stages of the layer transfer process are examined through transmission electron microscopy (TEM) from the initial hydrogen implant through the final Ge film polish. The completed GOI substrate is characterized for film uniformity, surface quality, contamination, stress, defectivity, and thermal robustness using a variety of techniques and found to be acceptable for initial device processing.     

用于MEMS器件芯片级封装的金-硅键合技术研究

MEMS器件大都含有可动的硅结构 ,在器件加工过程中 ,特别是在封装过程中极易受损 ,大大影响器件的成品率。如果能在MEMS器件可动结构完成以后 ,加上一层封盖保护 ,可以显著提高器件的成品率和可靠性。本文提出了一种用于MEMS芯片封盖保护的金 硅键合新结构 ,实验证明此方法简单实用 ,效果良好。该技术与器件制造工艺兼容 ,键合温度低 ,有足够的键合强度 ,不损坏器件结构 ,实现了MEMS器件的芯片级封装。我们已经将此技术成功地应用于射流陀螺的制造工艺中     

Fabrication of low defect density 3C-SiC on SiO2 structures using wafer bonding techniques

This paper reports on a process to fabricate single-crystal 3C-SiC on SiO₂ structures using a wafer bonding technique. The process uses the bonding of two polished polysilicon surfaces as a means to transfer a heteroepitaxial 3C-SiC film grown on a Si wafer to a thermally oxidized Si wafer. Transfer yields of up to 80% for 4 inch diameter 3C-SiC films have been achieved. Homoepitaxial 3C-SiC films grown on the 3C-SiC on SiO₂ structures have a much lower defect density than conventional 3C-SiC on Si films.     

Point defects generated by direct-wafer bonding of silicon

High-purity float zone (FZ) silicon p- and n-type wafers were directly bonded hydrophobically at 700°C and 1050°C. Electrical I-V and capacitance-voltage (C-V) characterization was performed on p-n junctions of 2-mm square chips cut out from properly bonded areas of the wafers. The point defects were investigated by Deep Level Transient Spectroscopy (DLTS). As expected, annealing at 700°C resulted in high void density, while at 1050°C void-free bonded structures were formed. The I-V characteristics were dominated by recombination at the bonded interface and by the resistance of the n-type wafer. The point defects identified by DLTS are divacancy, vacancy-phosphor, and vacancy-oxygen complexes. These defects explain qualitatively the observed characteristics of the samples.     

阳极连接中碱金属双离子迁移模型􀀂

在假设玻璃中仅有两种可动碱金属离子的情况下，提出了一个金属－玻璃电场辅助阳极连接模型。根据该模型，玻璃中的Na和K耗尽层厚度在演化过程中成比例，它们的演化规律决定于耗尽层边上的负电荷层。数据拟合结果表明，文献[4]中的Na、K耗尽层厚度与连接时间的关系可用时间的对数函数很好地描述。K富集层起因于K^ 离子的中和，Na耗尽导上的负电荷产生的电场引起了实验中测得K^ 离子跃迁激活能与Na^ 离子的激活能几乎相等。阳极连接过程中不存在稳态，总可观测到微小电流，该电流仍源于离子电导。     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

InP and Si metal-oxide semiconductor structures fabricated using oxygen plasma assisted wafer bonding

In this paper, InP metal-oxide-semiconductor (MOS) structures are fabricated by transferring thermally grown SiO₂ to InP from oxidized Si wafers using oxygen plasma assisted wafer bonding followed by annealing at either 125°C or at 400°C. Well-defined accumulation and inversion regions in recorded capacitance-voltage (C-V) curves were obtained. The long-term stability was comparable to what has been previously reported. The structures exhibited high breakdown fields, equivalent to thermally grown SiO₂-Si MOS structures. The transferring process was also used to fabricate bonded Si MOS structures.