亚辉光放电在HL—1装置的应用

本文简述亚辉光放电在HL-1装置上的应用。实验表明,这是一种安全、简便有效的清洗和碳化手段,它可以弥补磁控清洗放电和碳化的不足之处,并为HL-1M装置器壁锻炼提供了先行试验。     

HL-1工程联调中真空室的放电清洗

HL-1托卡马克装置工程联调时,内真空系统经200℃60小时烘烤和7万次脉冲放电清洗,接着作了124次低参数托卡马克放电。在环向磁场为15kG下获得了60kA的等离子体电流,等离子体存在时达85ms,本文总结分析了HL-1工程联调期间真空系统的烘烤、真空室的放电清洗技术及效果。     

HL-2M 装置初始等离子体放电阶段的直流辉光放电清洗系统研制

基于 HL-2M 托卡马克初始等离子体放电的工程需求,设计并研制了直流辉光放电清洗系统,包括电 极、馈线、电源、控制以及监测等关键部件和辅助子系统。研制完成后开展了系统装配和工程调试,并投入到首 次等离子体放电。实验结果表明,该直流辉光放电系统运行稳定、可靠,且此辉光放电清洗显著降低了真空室本 底杂质浓度,能满足 HL-2M 装置初始等离子体放电的壁条件需求。     

混合气体组合放电清洗在HL—1装置上的实验研究

在HL-1装置上进行混合气体H_2+H_e,H_2+N_e,H_2+K_r和N_2+X_e交流(50Hz)放电锻炼孔栏(1/8石墨,7/8钼)和GH39不锈钢真空室表面,其清洗效果明显地好于通常低功率纯氢气放电清洗(TDC,GDC和ECR-DC),并能有效地降低裸金属和碳化器壁表面氢气体库贮量,有利于托卡马克放电氢再循环控制,为高密度和低q放电提供了洁净的器壁和环境。上述混合气体交流放电结合2.45GHz电子回旋共振(ECR)放电,取得了更好的清洗效果。本文对这种高效、快速清洗方法的机制作了简单分析。     

HL-2M初始等离子体放电阶段的辉光放电清洗系统电极的设计与分析

针对HL-2M装置初始等离子体放电阶段所需的直流辉光放电清洗系统的电极进行了设计.对辉光放电清洗系统在不同工况下的系统负载进行了分析和拟定,并确定了电极结构设计分析标准.根据系统电极的结构特点并结合系统负载规范与分析标准,依据不同的失效模式对电极进行了失效分析.分析结果表明,此针对初始等离子体放电的电极设计能可靠安全运...     

HL—1M托卡马克装置的DC辉光放电清洗

本文简要叙述了ＨＬ－１Ｍ的ＤＣ辉光放电清洗技术和放电结果。实验表明，类似ＨＬ－１Ｍ托卡马克装置的真空室，经过烘烤，Ｔａｙｌｏｒ放电和ＤＣ放电清洗后，有可能得到高品质的等离子体。     

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建立了烘烤出气和辉光放电清洗(GDC)出气的物理模型,研究了装置器壁的烘烤出气和辉光放电清洗出气特点.烘烤出气是体出气,出气过程满足扩散方程;GDC出气是溅射脱附过程,它主要是器壁表面的溅射诱导出气.由此分析了HL-1M装置的烘烤出气和辉光放电清洗出气特点,得出了一些经验公式.     

HL—1装置杂质清除率的研究

本文比较了ECR,AC和TDC纯H_2放电清洗,TDC+ECR(AC)纯H_2组合放电清洗和ACH_2+Kr(Xe,Ne)混合气体放电清洗对HL-1装置真空壁的清洗效果;总结了1984—1989年度各种壁条件下,HL-1装置杂质平均清除率;从气体动力学方程出发,分析了实验结果。     

HL-2A装置真空系统

现代核聚变实验装置要求的真空系统必须实现以下主要功能：（1）装置真空室的零部件及总体抽空和检漏；（2）真空室的烘烤除气（H2O）；（3）辉光放电清洗和面对等离子体部件的锻炼及原位处理；（4）边缘粒子的抽运与控制；（5）等离子体放电实验运行。     

HL-2A托卡马克装置真空系统

介绍了HL 2A装置真空系统研制。它由真空主抽气系统、抽气偏滤器、直流辉光放电清洗系统组成。主抽气系统提供了装置真空室从大气到高真空、烘烤除气、直流辉光放电清洗所需要的抽气能力。抽气偏滤器初步实现了托卡马克放电过程中边缘粒子的抽运与控制;直流辉光放电清洗系统保证了装置良好的真空器壁条件。介绍了这些系统的初步运行情况,并给出了其测试结果。HL 2A装置首轮物理实验运行时真空室极限真空度达到4.6×10-6Pa,12h总漏放气率为1.8×10-5Pa·m3·s-1。     

Modeling of pulsed spark discharge in water and its application to well cleaning

This paper presents a simulation model for the generation of strong pressure wave by means of pulsed spark discharge in water and its application to well cleaning. In the simulation model, one-dimensional time-dependent magnetohydrodynamic equations are coupled to a capacitive discharge circuit equation. A cylindrical conducting spark channel formed by electrical breakdown of water gap between a pair of electrodes is treated as a load of which resistance and inductance are allowed to change with time. For describing the spark channel properties accurately, precise calculations on thermodynamic properties and electrical conductivity are included in the simulation model. The simulation results show an excellent agreement with the experimentally measured shock pressure as well as the current and voltage waveforms. The simulation reveals that Joule heating of the spark channel during the very early phase of electrical discharge plays a key role in the formation of shock wave in water. The voltage on a capacitor at breakdown, the circuit inductance, and the resistance of the spark channel are found to be the most important parameters for the shock wave formation. With this technique, a pilot test for the cleaning of a clogged well has been performed in a water well which was constructed as a test-bed for riverbank filtration near the Anseong-cheon (river) in Korea. Well treatments have been carried out with an electrical energy of 510 J stored on a pulsed power system, at which the maximum shock pressure is measured to be around 7 MPa at the position of the well screen, i.e. 0.1 m away from the spark gap. A slug test shows 2.9 times improvement in the hydraulic conductivity of the well, which, combined with a visual inspection inside the well using an underwater camera, clearly demonstrates that the strong pressure wave generated by underwater spark discharge can effectively remove almost all incrustations formed in the well screen and thus improve well performance. Operating parameters for controlling the strength of shock pressure are discussed using the simulation model for extensive applications of the present technique to various types of water wells.     

H_2辉光放电清洗时轰击器壁的离子能量测量与分析

一、引言 辉光放电是清洗锻炼环流器真空室器壁的有效手段。H_2辉光放电时,氢离子轰击器壁与器壁中的C和O发生化学反应,生成CH_4,H_2O等气体;同时,这些离子提供能量使得吸附在器壁表面的杂质气体脱附,从而被泵出真空室外,达到清洗锻炼的目的。由于辉光放电时,离子轰击的能量较高,会引起一定的溅射沉积。我们在模拟真空室(六通装置)进行了辉光放电,对各种参数下的离子能量进行了测量,从中找出了离子能量与极间电压(阳极与器壁之间的电压)、放电电流、以及气压、离子流密度之间的某些关系。     

Surface cleaning of metal wire by atmospheric pressure plasma

In this study, the possible application of atmospheric pressure dielectric barrier discharge plasma for the annealing of metallic wire is examined and presented. The main purpose of the current study is to examine the surface cleaning effect for a cylindrical object by atmospheric pressure plasma. The experimental setup consists of a gas tank, plasma reactor, and power supply with control panel. The gas assists in the generation of plasma. Copper wire was used as an experimental cylindrical object. This copper wire was irradiated with the plasma, and the cleaning effect was confirmed. The result showed that it is possible to remove the tarnish which exists on the copper wire surface. The experiment reveals that atmospheric pressure plasma is usable for the surface cleaning of metal wire. However, it is necessary to examine the method for preventing oxidization of the copper wire.     

间隙绝缘电极辉光放电实验观察

实验研究了ITER H2/He辉光放电壁处理(GDC)系统的电极合理的间隙绝缘参数及标定辉光过程中沉积在电极头部的热负载.进行了H2/He击穿电压特性试验,在ITER GDC预期的壁离子电流密度条件下研究了H2/He辉光放电电压和试验电极上热负荷与压强的关系、试验电极启辉耐受特性、试验电极温度与热负荷的关系以及在不同区...     

HL-1托卡马克放电辐照的因科镍和铝的表面效应研究

核聚变能是最有希望的一种新能源,我国自行设计与建造的核聚变装置——HL-1已于1985年投入运行。研究核聚变装置中等离子体与器壁、孔栏材料相互作用日益受到广泛重视,因为这种反应造成等离子体的污染及聚变装置材料灼损坏。同时,这一研究还将提供等离子体边界层的性能参数,为下一代装置的器壁材料选择和结构设计提供参考。本文研究了镍基合金和铝探针在HL-1装置的等离子体括削层内,经等离子体辐照后的表面形貌及表面组分的变化。     

DHR TDC芯片的性能测试

TDC(time-to-digital converter)作为基于信号甄别和时间数字转换的时间测量技术路线的主要组成部分之一,至今在诸多领域中都具有广泛的应用.本实验室对高精度时间测量TDC ASIC(Application Specific In-tegrated Circuit)进行了深入研究,在180nm CM...     

Effective suppression of pneumatic vibration isolators by using input-output linearization and time delay control

This paper presents a new state space representation of pneumatic vibration isolators (PVIs) and a design of a robust control, Time Delay Control (TDC), based on it. The new state space model, derived by using the input-output linearization method, is of the phase variable form with the air mass-flow as the control input. This model offers a framework that enables simultaneous suppression of both seismic vibration and direct disturbance (or payload disturbance) with an accelerometer only. Based on this model, TDC is designed and verified with experiments on a single chamber PVI with an accelerometer only. In the experiment, the PVI with TDC successfully suppresses seismic vibration and direct disturbance, both individually and simultaneously. Faced with seismic vibration, the transmissibility of the PVI with TDC has virtually no resonance peak at low frequency; under direct disturbance, the former achieves a 68 percent reduction in settling time of the latter. The final analysis of experimental result shows that TDC effectively estimates the modeling error along with other uncertainties and cancels them, while achieving desired closed-loop dynamics.     

TOT measurement implemented in FPGA TDC

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays(FPGAs), FPGA time-to-digital converters(TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold(TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.