毫米波频段下MOSFET漏极电流噪声的统一模型

纳米级金属氧化物半导体场效应晶体管(MOSFET)精确的高频噪声模型是毫米波集成电路低功耗设计的重要基础,而现有的高频漏极噪声模型不仅没有融合器件的衬底效应和栅电阻效应,也没有充分考虑器件的频率和偏置依赖性。针对上述问题,基于纳米MOSFET器件的物理特性,并结合漂移扩散方程和有效栅极过载,建立统一表征强反区到弱反区的频率和偏置依赖性的漏极噪声模型,使之便于移植到先进设计系统(ADS)仿真设计。通过所建模型的仿真结果与实验测试结果进行比较,验证所建模型的准确性。同时比较所建模型对130 nm和40 nm MOSFET两种不同工艺器件的实用性,验证其对表征40 nm MOSFET的毫米波噪声特性的优越性。     

短沟道金属-氧化物半导体场效应晶体管的散粒噪声模型

随着金属-氧化物半导体场效应晶体管(MOSFET)器件的尺寸进入到纳米量级,器件的噪声机理逐渐开始转变.传统的热噪声与漏源电流模型精度出现下降,散粒噪声成为器件噪声不可忽略的因素.本文通过求解能量平衡方程,推导了短沟道MOSFET器件的沟道电子温度和电子速度表达式,由此建立了漏源电流模型;基于漏源电流模型建立了适用于40 nm以下器件的散粒噪声模型和热噪声模型.研究了n型金属-氧化物半导体场效应晶体管(NMOSFET)器件在不同偏置电压下,器件尺寸对散粒噪声抑制因子和噪声机理的影响.研究表明:已有的热噪声模型与散粒噪声模型的精度随着器件尺寸的减小而下降,导致相应的散粒噪声抑制因子被高估.当NMOSFET器件的尺寸减小到10 nm时,器件的噪声需由热噪声与受抑制的散粒噪声共同表征.本文建立的短沟道器件散粒噪声模型可应用于纳米尺寸NMOSFET器件噪声性能的分析与建模.     

40nm金属氧化物半导体场效应晶体管感应栅极噪声及互相关噪声频率与偏置依赖性建模

用于低功耗、混合信号及高频领域的CMOS技术的缩比进展,表明其最佳的高频性能已从低中反区转移至弱反区.高频噪声模型是射频与毫米波电路设计的先决条件,是纳米级金属氧化物半导体场效应晶体管(MOSFET)噪声分析的重要基础.本文基于40 nm MOSFET的器件物理结构,并结合漂移-扩散方程和电荷守恒定律,提出了基于物理的高频感应栅极电流噪声模型及其与漏极电流噪声的互相关噪声模型,以此来统一表征噪声从弱反区到强反区的频率与偏置依赖性.本文通过将有效栅极过载引入高频噪声模型中,使得统一模型具有良好的准确性、连续性和平滑性.最后,通过所建模型的仿真结果与实验结果的数据比较,验证了本文所建模型的准确性及其对长沟道器件在强反区的适用性.     

45 nm MOSFET毫米波小信号等效电路模型参数提取技术

为了有效地表征45 nm MOSFET毫米波频段下的电学特性,研究了其高频等效电路的建模方法。基于45 nm MOSFET的器件物理结构及其导纳参数分析,通过综合考虑器件的本征物理特性、管脚及测试寄生特性,提出了一种准静态近似的高频等效电路模型及其参数直接提取的高精度简化算法,以此来统一表征模型参数从强反型区到弱反型区的偏置依赖性,并使之在不同偏置条件下的特性表征具有良好的连续性,以便于移植到商业仿真设计自动化工具中。通过ADS2013仿真工具的散射参数模拟结果与测量数据的一致性比较,验证了所建模型的实用性及其参数提取算法的准确性, 并表征了45 nm器件的偏置依赖性。     

一个圆柱形双栅场效应晶体管的物理模型

圆柱形双栅场效应晶体管(CSDG MOSFET)是在围栅MOSFET器件增加内部控制栅而形成,与双栅、三栅及围栅MOSFET器件相比,圆柱形双栅MOSFET提供了更好的栅控性能和输出特性.本文通过求解圆柱坐标系下的二维泊松方程,得到了圆柱形双栅MOSFET的电势模型;进一步对反型电荷沿沟道积分,建立其漏源电流模型.分析讨论了圆柱形双栅MOSFET器件的电学特性,结果表明:圆柱形双栅MOSFET外栅沿沟道的最小表面势和器件的阈值电压随栅介质层介电常数的增大而减小,其漏源电流和跨导随栅介质层介电常数的增大而增大;随着器件参数的等比例缩小,沟道反型电荷密度减小,其漏源电流和跨导也减小.     

非晶铟锌氧化物薄膜晶体管的低频噪声特性与分析

本文针对底栅结构非晶铟锌氧化物薄膜晶体管的低频噪声特性开展实验与理论研究.由实验结果可知:受铟锌氧化物与二氧化硅界面处缺陷态俘获与释放载流子效应的影响,器件沟道电流噪声功率谱密度随频率的变化遵循1/fγ(γ≈0.75)的变化规律;此外,器件沟道电流归一化噪声功率谱密度随沟道长度与沟道宽度的增加而减小,证明器件低频噪声来源于沟道的闪烁噪声,可忽略源漏结接触及寄生电阻对器件低频噪声的影响.最后,基于载流子数涨落及迁移率涨落模型,提取γ因子与平均Hooge因子,为评价材料及器件特性奠定基础.     

纳米尺度MOSFET过剩噪声的定性分析

最近实验表明纳米尺度MOSFET中的过剩噪声主要为散粒噪声,而此前研究认为MOSFET中不存在散粒噪声,短沟道MOSFET中的过剩噪声为热噪声. 本文基于器件电流模型分析散粒噪声取代热噪声成为过剩噪声主要成分的转变条件,根据该条件对纳米尺度MOSFET噪声特性的预测与文献报道的实验现象、模拟结果以及介观散粒噪声相关结论相符合. 关键词： 散粒噪声 过剩噪声 纳米尺度MOSFET     

6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

10 nm金属氧化物半导体场效应晶体管中的热噪声特性分析

随着金属氧化物半导体场效应晶体管(MOSFET)器件等比例缩小至纳米级的较小尺寸,一方面导致的短沟道效应已严重影响热噪声;另一方面使栅、源、漏区及衬底区的热噪声占有比越来越高,而传统热噪声模型主要考虑较大尺寸器件的沟道热噪声,且其模型未考虑到沟道饱和区.本文针对小尺寸纳米级MOSFET器件,并根据器件结构特征和热噪声的基本特性,建立了10 nm器件的热噪声模型,该模型体现沟道区、衬底区及栅、源、漏区,同时考虑到沟道饱和区的热噪声.在模型的基础上,分析沟道热噪声、总热噪声随偏置参量及器件参数之间的关系,验证了沟道饱和区热噪声的存在,并与已有实验结果一致,所得结论有助于提高纳米级小尺寸MOSFET器件的工作效率、寿命及响应速度等.     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

Observation of nonconservation characteristics of radio frequency noise mechanism of 40-nm n-MOSFET

Bias non-conservation characteristics of radio-frequency noise mechanism of 40-nm n-MOSFET are observed by modeling and measuring its drain current noise. A compact model for the drain current noise of 40-nm MOSFET is proposed through the noise analysis. This model fully describes three kinds of main physical sources that determine the noise mechanism of 40-nm MOSFET, i.e., intrinsic drain current noise, thermal noise induced by the gate parasitic resistance, and coupling thermal noise induced by substrate parasitic effect. The accuracy of the proposed model is verified by noise measurements, and the intrinsic drain current noise is proved to be the suppressed shot noise, and with the decrease of the gate voltage, the suppressed degree gradually decreases until it vanishes. The most important findings of the bias non-conservative nature of noise mechanism of 40-nm n-MOSFET are as follows.(i) In the strong inversion region, the suppressed shot noise is weakly affected by the thermal noise of gate parasitic resistance. Therefore, one can empirically model the channel excess noise as being like the suppressed shot noise.(ii) In the middle inversion region, it is almost full of shot noise.(iii) In the weak inversion region, the thermal noise is strongly frequency-dependent, which is almost controlled by the capacitive coupling of substrate parasitic resistance. Measurement results over a wide temperature range demonstrate that the thermal noise of 40-nm n-MOSFET exists in a region from the weak to strong inversion, contrary to the predictions of suppressed shot noise model only suitable for the strong inversion and middle inversion region. These new findings of the noise mechanism of 40-nm n-MOSFET are very beneficial for its applications in ultra low-voltage and low-power RF, such as novel device electronic structure optimization, integrated circuit design and process technology evaluation.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.     

MOSFET scaling into the 10 nm regime

Scaling limits of the double-gate MOSFET structure are explored. Because short-channel effects can be adequately controlled by thinning the silicon body, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain. Depending on threshold voltage and the source/drain doping profile, this will restrict gate length scaling to 5–11 nm. As power supplies are scaled down, maintaining on-state drive current may become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device performance may still be improved.     

Field-induced generation-recombination noise in (100) n-channel Si-MOSFET's at T = 4.2 K: II. Experiments

The spectral noise intensity of the drain current of an n-channel (100) Si-MOSFET in strong inversion was measured as a function of drain current and gate voltage at T = 4.2 K. In addition to flicker noise and white noise it was possible to distinguish a Lorentzian, which was due to generation-recombination noise. Since, at T = 4.2 K, the 2D-electron gas in the MOSFET in strong inversion is degenerate this generation-recombination noise must be caused by traps in the conduction band. The measured noise relaxation time was found to depend on drain current.Our results can be interpreted in terms of a generation-recombination process in which the generation is partly field-induced. Agreement between theory and experiment is within the experimental error, both for the way in which the inverse noise relaxation time depends on drain current and the way in which the ratio of the low frequency plateau of the spectral noise intensity to the noise relaxation time depends on the product of drain current and drain voltage. Measurements of the ratio of the low-frequency plateau of the spectral noise intensity to the relaxation time versus gate voltage at T = 4.2 K we used to construct an energy spectrum of the density of traps in the conduction band. A maximum is observed at about 14meV above the bottom of the conduction band.     

固态Marx发生器的过流保护研究

具有快速上升沿、低开关损耗的SiC MOSFET已逐渐在固态高压脉冲电源中使用。针对固态Marx发生器中的常见短路故障,分析了SiC MOSFET的过流损坏机制,提出了一种新型的带过流保护的驱动系统。该驱动系统不仅实现了宽驱动信号同步输出,同时能够在整个SiC MOSFET导通期间提供过电流钳制效果。驱动系统中的保护电路利用SiC MOSFET门极电压与漏极电流的关系,通过单个采样电阻和一对反向串联的稳压管将SiC MOSFET门极电压拉低的方式来限制过电流。实验结果表明:当开关管的导通电流较小时,虽然门极电压会有轻微下降,但是SiC MOSFET的导通阻抗仍然很低;而在过电流故障发生时,门极电压会被快速拉低,开关管的导通阻抗急剧上升,从而迅速将导通电流钳制在安全范围内。     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.