SiO2固态电解质中的质子特性对氧化物双电层薄膜晶体管性能的影响

本文采用等离子体增强化学气相沉积技术(PECVD)在室温条件下制备了具有双电层效应的二氧化硅(SiO₂) 固体电解质薄膜, 并以此SiO₂薄膜作为栅介质制备了氧化铟锌(IZO)双电层薄膜晶体管. 本文系统地研究了SiO₂固体电解质中的质子特性对双电层薄膜晶体管性能的影响, 研究结果表明, 经过纯水浸泡的SiO₂固体电解质薄膜可以诱导出较多的可迁移质子, 因此表现出较大的双电层电容. 由于SiO₂固体电解质薄膜具有质子迁移特性, 晶体管的转移特性曲线呈现出逆时针方向的洄滞现象, 并且这一洄滞效应随着栅极电压扫描速率的增加而增大. 进一步对薄膜晶体管的偏压稳定性进行测试, 发现晶体管的阈值电压的变化遵循了拉升指数函数(stretched exponential function)关系.     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

Thermal annealing and channel composition influences on the electrical properties of transparent-TFTs based on Zn-In-SnO ternary compound: Experiment and modeling

In this study, we present a quantitative analysis of the electrical properties of a series of bottom- gate top-contact n-channel transparent thin film transistors (TFTs) based on zinc indium tin oxide (Zn-In-SnO) ternary compound with various ZnO content. In addition, the effect of annealing on the TFTs electrical properties was examined theoretically and experimentally. The obtained results revealed that the thermal annealing of fabricated devices in air atmosphere at 300°C has enhanced their performances; this behavior is well observed for all devices fabricated with different composition of Zn-In-SnO. TFTs having the lowest Zn content of 17.1% and annealed 300^°C showed the high electrical performances in term of drain current, saturation mobility, threshold voltage. For the total resistance modeling of the fabricated devices with various content of ZnO and that annealed 300 ^°C, grain boundary model based on Meyer–Neldel rule was applied. The obtained results revealed that the total resistance was increased with increasing ZnO content. Furthermore, an analytical model has been refined in order to reproduce the current-voltage relationships of the fabricated TFTs using the overall resistance obtained from the NMR–GBT model. The calculated results are in good agreement with the experimental measurements of all fabricated devices. The obtained performance of TFTs based on zinc indium tin oxide with low content of ZnO and annealed will be promising for application in the future backplane of flat panel displays.     

基于SOI材料α-Si:H TFTs的制作和特性研究

采用RF-PECVD系统在SOI材料上制作-Si:H TFT,纳米非晶硅薄膜厚度为98 nm,沟道长宽比为10 m/40 m。用扫描电子显微镜、X射线衍射和拉曼光谱等检测方法对不同退火温度下的氢化非晶硅薄膜形貌进行了表征。采用CMOS工艺、各向异性腐蚀溶液EPW、射频溅射技术和等离子体刻蚀等工艺实现-Si:H TFT的制作。在给出一般-Si:H TFT特性分析和实验结果的基础上,又采用建模方式对-Si:H TFT出现的负阻特性进行研究。提取纳米氢化非晶硅薄膜与栅氧化层界面处能带图的结果表明,在靠近漏端0.5 m范围内,漏压由6 V增加到30 V时,随漏压的增加,价带能量逐渐下降。研究结果表明,距离漏端0.5 m范围内的压降导致负阻特性产生。     

Hydrogenation effect on silicon on sapphire grown by rapid thermal chemical vapor deposition

Single crystalline Si epilayers were grown on sapphire substrates through a three-step growth method by rapid thermal chemical vapor deposition (RTCVD). Hydrogenation of the epilayers was performed by the hydrogen-plasma exposure (HPE) in a remote plasma chemical vapor deposition (RPCVD) system, following rapid thermal annealing. It was found that the hydrogenation treatment improves the crystallinity of the Si epilayer as well as the electrical properties of Si epilayers. After hydrogenation, especially, the intensity of the deep level defects which are responsible for the lattice mismatch between Si and the sapphire substrate decreases. Also, dislocations and microtwins are reduced remarkably, improving the crystallinity. In Schottky diodes fabricated on hydrogenation-processed Si epilayers, the leakage current decreases one order of magnitude in comparison to non-hydrogenated samples. It is suggested that these characteristics could be explained by the hydrogen incorporation at defects.     

金属诱导单一方向横向晶化薄膜晶体管以及栅控型轻掺杂漏极结构的研究

提出了一种低温金属单向诱导横向晶化的多晶硅薄膜晶体管(LT-MIUC poly-Si TFT) 的技术 . 使用该技术可在大面积廉价玻璃衬底上制备出高迁移率、低漏电电流、具有较好均匀性的 多晶硅器件. 在进一步的研究中，设计了一种新型的栅控轻掺杂漏区(GM-LDD)结构，有效地 解决了在较高源漏电压下的栅诱导漏电问题. 使得LT-MIUC poly-Si TFT 更适用于高质量的 有源矩阵显示器. 关键词： 金属单向诱导横向晶化 多晶硅薄膜晶体管 新型栅控轻掺杂漏区结构     

基于氧化铟锡的无结低电压薄膜晶体管

在室温下制备了基于氧化铟锡(ITO)的底栅结构无结薄膜晶体管. 源漏电极和沟道层都是同样的ITO薄膜材料,没有形成传统的源极结和漏极结, 因而极大的简化了制备流程,降低了工艺成本.使用具有大电容的双电荷层SiO₂作为栅介质, 发现当ITO沟道层的厚度降到约20 nm时, 器件的栅极电压可以很好的调控源漏电流. 这些无结薄膜晶体管具有良好的器件性能: 低工作电压(1.5 V), 小亚阈值摆幅(0.13 V/dec)、 高迁移率(21.56 cm²/V·s)和大开关电流比(1.3× 10⁶). 这些器件即使直接在大气环境中放置4个月, 器件性能也没有明显恶化:亚阈值摆幅保持为0.13 V/dec,迁移率略微下降至18.99 cm²/V·s,开关电流比依然大于10⁶.这种工作电压低、工艺简单、 性能稳定的无结低电压薄膜晶体管非常有希望应用于低能耗便携式电子产品以及新型传感器领域.     

非晶铟镓锌氧薄膜晶体管钼/铜源漏电极的研究

针对非晶铟镓锌氧薄膜晶体管（a-IGZO TFT）的钼/铜源漏电极开展研究。实验证明,单层Mo源漏电极与栅绝缘层之间的粘附性好、表面粗糙度较小、电阻率较大,而单层Cu源漏电极与栅绝缘层之间的结合性差且Cu原子扩散问题严重、表面粗糙度较大、电阻率较小。为了实现优势互补,我们设计了双层Mo（20 nm）/Cu（80 nm）源漏电极,并采用优化工艺制备了包含该电极结构的a-IGZO TFT。器件具有良好的电学特性,场效应迁移率为 8.33 cm²·V^-1·s^-1, 阈值电压为6.0 V,亚阈值摆幅为2.0 V/dec,开关比为 1.3×10⁷,证明了双层Mo/Cu源漏电极的可行性和实用性。     

退火温度对新型有源层WZTO薄膜晶体管性能的影响

通过溶液法制备了新型有源层钨锌锡氧化物(WZTO)薄膜晶体管(TFT),研究了不同退火温度对WZTO薄膜和TFT器件性能的影响。XRD结果表明即使退火温度达到500℃,WZTO薄膜仍为非晶态结构。W掺杂显著降低了薄膜表面粗糙度,其粗糙度均从0. 9 nm降低到0. 5 nm以下;但不影响薄膜可见光透过率,其透过率均大于85%。同时XPS分析证实随退火温度升高,WZTO薄膜中对应氧空位的峰增加。制备的WZTO器件阈值电压由8. 04 V降至3. 48 V,载流子迁移率随着退火温度的升高而增大,开关电流比达到107。     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Current noise in (111) n-channel Si-MOSFET's at T = 4.2 K

We have investigated the drain current-drain voltage characteristics and the spectral noise intensity of the drain current of (111) n-channel MOSFET's at T = 4.2 K. At T = 4.2 K the drain current-drain voltage characteristics showed a hysteresis which was not observed at T =77 K and at room temperature. A qualitative explanation of this hysteresis is given in terms of electron transfer from high mobility valleys to low mobility valleys due to hot electrons. In the spectra of the current noise three contributions could be distinguished: 1/ƒ-noise, white noise and generation-recombination noise. The 1/ƒ-noise is interpreted as number fluctuations noise. The effective trap density was found to be 2.3 × 10²² m^-3. At low drain voltages the white noise can be interpreted as diffusion noise. At higher drain voltages extra noise is observed over and above diffusion noise. This extra noise may be inter-valley noise. The generation-recombination noise was very sensitive to the gate voltage. A tentative explanation can be given if it is assumed that the traps which cause this noise have a non-uniform energy distribution.     

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V_ds of 5.0 V is suppressed, whereas the drain leakage current at V_ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.     

退火温度对溶胶-凝胶法制备锌锡氧化物薄膜晶体管的影响

采用溶胶-凝胶法制备了非晶锌锡氧化物(ZTO)薄膜晶体管(TFT),通过热重-差热分析(TG-DTA)对ZTO胶体中的化学反应进行了分析,研究了不同退火温度对ZTO TFTs性能的影响。结果表明:当退火温度在300~500℃范围内时,薄膜为非晶态结构,薄膜表面致密、平整。当退火温度达到400℃时,薄膜在可见光范围内具有高透过率(>85%)。随着退火温度的升高,器件阈值电压明显降低,由15.85 V降至3.76 V,载流子迁移率由0.004 cm²·V^-1·s^-1提高到5.16 cm²·V^-1·s^-1,开关电流比达到10⁵。退火温度的升高明显改善了ZTO TFT的电学性能。     

氢元素对铟镓锌氧化物薄膜晶体管性能的影响

对国际上有关铟镓锌氧化物薄膜晶体管中氢元素的来源、存在形式、表征方法以及对器件性能的影响进行了综述.氢元素是铟镓锌氧化物薄膜晶体管中最为常见的杂质元素,能以正离子和负离子两种形式存在于薄膜晶体管的沟道中,并对器件性能和电学可靠性产生影响.对铟镓锌氧化物薄膜晶体管而言,沟道中氢元素浓度越高,其场效应迁移率越高、亚阈值摆幅越小、器件的电学稳定性也越好.同时,工艺处理温度过低或过高都不利于其器件性能的改善,通常以200—300?C为宜.     

退火温度对非晶铟钨氧薄膜晶体管特性的影响

非晶铟钨氧(a-IWO)薄膜晶体管(TFT)具有高迁移率和高稳定性的优点,但其适合于实际生产的制备工艺条件尚有待摸索。本文研究了退火温度对a-IWO TFT电学特性影响的基本规律和内部机理。实验结果表明,随着退火温度的升高,a-IWO TFT的场效应迁移率也相应增加,这是由于高温退火下a-IWO薄膜中氧空位含量增多并进而导致载流子浓度增加的缘故。此外,a-IWO TFT的亚阈值摆幅和阈值电压在200℃下退火达到最佳,我们认为主要原因在于此时a-IWO薄膜的表面粗糙度最小并形成了最佳的前沟道界面状态。     

Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN HEMT

A two-dimensional (2-D) analytical model for a Dual Material Gate (DMG) AlGaN/GaN High Electron Mobility Transistor (HEMT) has been developed to demonstrate the unique attributes of this device structure in suppressing short channel effects (SCEs). The model accurately predicts the channel potential, electric field variation along the channel, and sub-threshold drain current, taking into account the effect of lengths of the two gate metals, their work functions, barrier layer thicknesses, and applied drain biases. It is seen that the SCEs and hot carrier effects in DMG AlGaN/GaN HEMT are suppressed due to the work function difference of the two metal gates, thereby screening the drain potential variations by the gate near the drain. Besides, a more uniform electric field along the channel leads to improved carrier transport efficiency. The accuracy of the results obtained from our analytical model has been verified using ATLAS device simulations.     

基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压     

A thin-film transistor with a very thin a-Si:H layer and its application for an LC panel

One of the disadvantages of applying an a-Si:H thin-film transistor (TFT) to an active matrix-addressed liquid crystal (LC) panel is that a TFT with an a-Si:H has a very large photo-leakage current because of the high photo-conductivity of an a-Si:H itself.We have tried decreasing the photo-leakage current by varying the thickness of an a-Si:H layer (L) in TFTs and investigated the characteristics of TFTs, mainly drain voltage versus drain current containing photo-leakage current (I _ph).As a result, it is shown that lnI _ph is proportional to InL, and its gradient is 1.5–2.0. We assume that the thinner an a-Si:H layer is, the more effective the recombination of carriers at the interface states is forI _ph.We have applied TFT with a very thin a-Si:H layer (30nm) to a full-color active matrix-addressed LC panel for a moving picture display and realized a display of good quality under illuminated condition of 5×10⁴lx without a shading layer in it.     

Novel carbon nanotube field effect transistor with graded double halo channel

A novel carbon nanotube field effect transistor with symmetric graded double halo channel (GDH–CNTFET) is presented for suppressing band to band tunneling and improving the device performance. GDH structure includes two symmetric graded haloes which are broadened throughout the channel. The doping concentration of GDH channel is at maximum level at drain/source side and is reduced gradually toward zero at the middle of channel. The doping distribution at source side of channel reduces the drain induced barrier lowering (DIBL) and the drain side suppresses the band to band tunneling effect. In addition, broadening the doping throughout the channel increases the recombination of electrons and holes and acts as an additional factor for improving the band to band tunneling. Simulation results show that applying this structure on CNTFET enhances the device performance. In comparison with double halo structure with equal saturation current, the proposed GDH structure shows better characteristics and short channel parameters. Furthermore, the delay and power delay product (PDP) analysis versus on/off current ratio shows the efficiency of the proposed GDH structure.     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)